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Class Information
Number: 257/E21.243
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic technique (epo) > Post-treatment (epo) > Planarization of insulating layer (epo)
Description: This subclass is indented under subclass E21.241. This subclass is substantially the same in scope as ECLA classification H01L21/3105B.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.244 Involving dielectric removal step (epo) 942


Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
5629224 Resist/etchback planarizing techniques for fabricating semiconductor devices based on CMOS structures May. 13, 1997
5605867 Method of manufacturing insulating film of semiconductor device and apparatus for carrying out the same Feb. 25, 1997
5598028 Highly-planar interlayer dielectric thin films in integrated circuits Jan. 28, 1997
5531834 Plasma film forming method and apparatus and plasma processing apparatus Jul. 2, 1996
5508233 Global planarization process using patterned oxide Apr. 16, 1996
5503882 Method for planarizing an integrated circuit topography Apr. 2, 1996
5498574 Process of fabricating semiconductor device having flattening stage for inter-level insulating layer without deterioration of device characteristics Mar. 12, 1996
5496776 Spin-on-glass planarization process with ion implantation Mar. 5, 1996
5492864 Method and equipment for manufacturing a semiconductor device Feb. 20, 1996
5489553 HF vapor surface treatment for the 03 teos gap filling deposition Feb. 6, 1996
5473187 Hybrids semiconductor circuit Dec. 5, 1995
5470801 Low dielectric constant insulation layer for integrated circuit structure and method of making same Nov. 28, 1995
5448111 Semiconductor device and method for fabricating the same Sep. 5, 1995
5445996 Method for planarizing a semiconductor device having a amorphous layer Aug. 29, 1995
5434107 Method for planarization Jul. 18, 1995
5426058 Method of manufacturing solid-state imaging device Jun. 20, 1995
5426076 Dielectric deposition and cleaning process for improved gap filling and device planarization Jun. 20, 1995
5405807 Semiconductor hybrids and method of making same Apr. 11, 1995
5395785 SRAM cell fabrication with interlevel dielectric planarization Mar. 7, 1995
5384288 Method of forming a planarized insulation layer Jan. 24, 1995
5372974 Approach to avoid buckling in BPSG by using an intermediate barrier layer Dec. 13, 1994
5371046 Method to solve sog non-uniformity in the VLSI process Dec. 6, 1994
5364818 Sog with moisture resistant protective capping layer Nov. 15, 1994
5352630 Method for forming inter-metal dielectrics in a semiconductor device Oct. 4, 1994
5348615 Selective planarization method using regelation Sep. 20, 1994
5344797 Method of forming interlevel dielectric for integrated circuits Sep. 6, 1994
5331117 Method to improve interlevel dielectric planarization Jul. 19, 1994
5320708 Dry etching method Jun. 14, 1994
5320983 Spin-on glass processing technique for the fabrication of semiconductor devices Jun. 14, 1994
5310720 Process for fabricating an integrated circuit device by forming a planarized polysilazane layer and oxidizing to form oxide layer May. 10, 1994
5294562 Trench isolation with global planarization using flood exposure Mar. 15, 1994
5285102 Method of forming a planarized insulation layer Feb. 8, 1994
5284804 Global planarization process Feb. 8, 1994
5281555 Method for alleviating the step difference in a semiconductor and a semiconductor device Jan. 25, 1994
5278103 Method for the controlled formation of voids in doped glass dielectric films Jan. 11, 1994
5275977 Insulating film forming method for semiconductor device interconnection Jan. 4, 1994
5270231 Method of manufacturing device having ferroelectric film Dec. 14, 1993
5268333 Method of reflowing a semiconductor device Dec. 7, 1993
5256593 Method of making isolation structure in semiconductor integrated circuit device Oct. 26, 1993
5254214 Plasma taper etching for semiconductor device fabrication Oct. 19, 1993
5244839 Semiconductor hybrids and method of making same Sep. 14, 1993
5187121 Process for fabrication of a semiconductor structure and contact stud Feb. 16, 1993
5175122 Planarization process for trench isolation in integrated circuit manufacture Dec. 29, 1992
5079178 Process for etching a metal oxide coating and simultaneous deposition of a polymer film, application of this process to the production of a thin film transistor Jan. 7, 1992
5004704 Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer Apr. 2, 1991
4952524 Semiconductor device manufacture including trench formation Aug. 28, 1990
4885262 Chemical modification of spin-on glass for improved performance in IC fabrication Dec. 5, 1989
4874463 Integrated circuits from wafers having improved flatness Oct. 17, 1989
4867838 Planarization through silylation Sep. 19, 1989
4816112 Planarization process through silylation Mar. 28, 1989

1 2 3 4 5 6










 
 
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