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Class Information
Number: 257/E21.243
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic technique (epo) > Post-treatment (epo) > Planarization of insulating layer (epo)
Description: This subclass is indented under subclass E21.241. This subclass is substantially the same in scope as ECLA classification H01L21/3105B.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.244 Involving dielectric removal step (epo) 942

Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
6753607 Structure for improving interlevel conductor connections Jun. 22, 2004
6749765 Aperture fill Jun. 15, 2004
6743728 Method for forming shallow trench isolation Jun. 1, 2004
6716767 Contact planarization materials that generate no volatile byproducts or residue during curing Apr. 6, 2004
6707134 Semiconductor structure having an improved pre-metal dielectric stack and method for forming the same Mar. 16, 2004
6703321 Low thermal budget solution for PMD application using sacvd layer Mar. 9, 2004
6690044 Approach to avoid buckling BPSG by using an intermediate barrier layer Feb. 10, 2004
6677252 Methods for planarization of non-planar surfaces in device fabrication Jan. 13, 2004
6660177 Apparatus and method for reactive atom plasma processing for material deposition Dec. 9, 2003
6660627 Method for planarization of wafers with high selectivities Dec. 9, 2003
6638878 Film planarization for low-k polymers used in semiconductor structures Oct. 28, 2003
6630739 Planarization structure and method for dielectric layers Oct. 7, 2003
6627549 Methods for making nearly planar dielectric films in integrated circuits Sep. 30, 2003
6620534 Film having enhanced reflow characteristics at low thermal budget Sep. 16, 2003
6589889 Contact planarization using nanoporous silica materials Jul. 8, 2003
6558756 Method of forming interlayer insulating film May. 6, 2003
6555910 Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof Apr. 29, 2003
6544858 Method for treating silicon-containing polymer layers with plasma or electromagnetic radiation Apr. 8, 2003
6541401 Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate Apr. 1, 2003
6541085 Tubular molded product using nylon 12 Apr. 1, 2003
6532772 Formation of planar dielectric layers using liquid interfaces Mar. 18, 2003
6527910 Staggered in-situ deposition and etching of a dielectric layer for HDP-CVD Mar. 4, 2003
6514876 Pre-metal dielectric rapid thermal processing for sub-micron technology Feb. 4, 2003
6514882 Aggregate dielectric layer to reduce nitride consumption Feb. 4, 2003
6509627 Flowable germanium doped silicate glass for use as a spacer oxide Jan. 21, 2003
6504234 Semiconductor device with interlayer film comprising a diffusion prevention layer to keep metal impurities from invading the underlying semiconductor substrate Jan. 7, 2003
6503843 Multistep chamber cleaning and film deposition process using a remote plasma that also enhances film gap fill Jan. 7, 2003
6492282 Integrated circuits and manufacturing methods Dec. 10, 2002
6489254 Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG Dec. 3, 2002
6479405 Method of forming silicon oxide layer in semiconductor manufacturing process using spin-on glass composition and isolation method using the same method Nov. 12, 2002
6461717 Aperture fill Oct. 8, 2002
6432839 Film forming method and manufacturing method of semiconductor device Aug. 13, 2002
6426015 Method of reducing undesired etching of insulation due to elevated boron concentrations Jul. 30, 2002
6413870 Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby Jul. 2, 2002
6407006 Method for integrated circuit planarization Jun. 18, 2002
6403499 Planarization of non-planar surfaces in device fabrication Jun. 11, 2002
6391798 Process for planarization a semiconductor substrate May. 21, 2002
6383949 Method of depositing an ozone-TEOS oxide film to eliminate its base material dependence, and apparatus for forming such a film at several different temperatures May. 7, 2002
6375790 Adaptive GCIB for smoothing surfaces Apr. 23, 2002
6318124 Nanoporous silica treated with siloxane polymers for ULSI applications Nov. 20, 2001
6319847 Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique Nov. 20, 2001
6313044 Methods for forming a spin-on-glass layer Nov. 6, 2001
6300653 Method for forming a high areal capacitance planar capacitor Oct. 9, 2001
6291367 Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer Sep. 18, 2001
6277441 Method of forming coating film on a substrate Aug. 21, 2001
6277754 Method of planarizing dielectric layer Aug. 21, 2001
6278151 Semiconductor device having wiring detour around step Aug. 21, 2001
6274479 Flowable germanium doped silicate glass for use as a spacer oxide Aug. 14, 2001
6271150 Methods of raising reflow temperature of glass alloys by thermal treatment in steam, and microelectronic structures formed thereby Aug. 7, 2001
6268297 Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces Jul. 31, 2001

1 2 3 4 5 6

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