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Class Information
Number: 257/E21.241
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic technique (epo) > Post-treatment (epo)
Description: This subclass is indented under subclass E21.24. This subclass is substantially the same in scope as ECLA classification H01L21/3105.


Sub-classes under this class:

Class Number Class Name Patents
257/E21.247 Doping insulating layer (epo) 39
257/E21.249 Etching insulating layer by chemical or physical means (epo) 28
257/E21.242 Of organic layer (epo) 167
257/E21.243 Planarization of insulating layer (epo) 240


Patents under this class:
1 2 3 4 5 6 7 8 9 10

Patent Number Title Of Patent Date Issued
7569499 Semiconductor device made by multiple anneal of stress inducing layer Aug. 4, 2009
7537971 Method for fabricating CMOS image sensor May. 26, 2009
7538001 Transistor gate forming methods and integrated circuits May. 26, 2009
7507677 Removable amorphous carbon CMP stop Mar. 24, 2009
7479465 Transfer of stress to a layer Jan. 20, 2009
7459391 Semiconductor device and method of fabricating the same Dec. 2, 2008
7405168 Plural treatment step process for treating dielectric films Jul. 29, 2008
7396724 Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals Jul. 8, 2008
7323729 Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor Jan. 29, 2008
7312138 Semiconductor device and method of manufacture thereof Dec. 25, 2007
7262142 Semiconductor device fabrication method Aug. 28, 2007
7223705 Ambient gas treatment of porous dielectric May. 29, 2007
7074625 Semiconductor device and method of manufacturing the same Jul. 11, 2006
7064052 Method of processing a transistor gate dielectric film with stem Jun. 20, 2006
7056835 Surface preparation prior to deposition Jun. 6, 2006
7052997 Method to form etch and/or CMP stop layers May. 30, 2006
7030023 Method for simultaneous degas and baking in copper damascene process Apr. 18, 2006
7030009 Method for forming metal interconnect in a carbon containing silicon oxide film Apr. 18, 2006
7022602 Nitrogen-enriched low-k barrier layer for a copper metallization layer Apr. 4, 2006
7022623 Method of fabricating a semiconductor device with a dielectric film using a wet oxidation with steam process Apr. 4, 2006
7015567 Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure Mar. 21, 2006
7015150 Exposed pore sealing post patterning Mar. 21, 2006
6979649 Fabrication method of semiconductor integrated circuit device Dec. 27, 2005
6979848 Memory system with conductive structures embedded in foamed insulator Dec. 27, 2005
6962855 Method of forming a porous material layer in a semiconductor device Nov. 8, 2005
6958277 Surface preparation prior to deposition Oct. 25, 2005
6949477 Method of fabricating a capacitive element for a semiconductor device Sep. 27, 2005
6943077 Selective spacer layer deposition method for forming spacers with different widths Sep. 13, 2005
6933246 Dielectric film Aug. 23, 2005
6921727 Method for modifying dielectric characteristics of dielectric layers Jul. 26, 2005
6921712 Process for producing integrated circuits including reduction using gaseous organic compounds Jul. 26, 2005
6911405 Semiconductor device and method of manufacturing the same Jun. 28, 2005
6911686 Semiconductor memory device having planarized upper surface and a SiON moisture barrier Jun. 28, 2005
6900128 Activation of oxides for electroless plating May. 31, 2005
6900118 Method for preventing contact defects in interlayer dielectric layer May. 31, 2005
6900121 Laser thermal annealing to eliminate oxide voiding May. 31, 2005
6893985 UV-activated dielectric layer May. 17, 2005
6887795 Method of growing electrical conductors May. 3, 2005
6887800 Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction May. 3, 2005
6878628 In situ reduction of copper oxide prior to silicon carbide deposition Apr. 12, 2005
6878602 Dielectric cure for reducing oxygen vacancies Apr. 12, 2005
6878644 Multistep cure technique for spin-on-glass films Apr. 12, 2005
6872671 Insulators for high density circuits Mar. 29, 2005
6872979 Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers Mar. 29, 2005
6869862 Method for improving a physical property defect value of a gate dielectric Mar. 22, 2005
6867126 Method to increase cracking threshold for low-k materials Mar. 15, 2005
6858923 Post-deposition treatment to enhance properties of Si-O-C low films Feb. 22, 2005
6849494 Dielectric cure for reducing oxygen vacancies Feb. 1, 2005
6846757 Dielectric layer for a semiconductor device and method of producing the same Jan. 25, 2005
6838300 Chemical treatment of low-k dielectric films Jan. 4, 2005

1 2 3 4 5 6 7 8 9 10


 
 
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