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Class Information
Number: 257/E21.236
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > Chemical or electrical treatment, e.g., electrolytic etching (epo) > Using mask (epo) > Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (epo) > Process specially adapted to improve resolution of mask (epo)
Description: This subclass is indented under subclass E21.233. This subclass is substantially the same in scope as ECLA classification H01L21/308D6.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8629064 Multiple patterning lithography using spacer and self-aligned assist patterns Jan. 14, 2014
8623770 Method for sidewall spacer line doubling using atomic layer deposition of a titanium oxide Jan. 7, 2014
8486840 Inverse spacer processing Jul. 16, 2013
8358010 Method for realizing a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method Jan. 22, 2013
8232211 Methods for self-aligned self-assembled patterning enhancement Jul. 31, 2012
8018070 Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devices Sep. 13, 2011
7951723 Integrated etch and supercritical CO.sub.2 process and chamber design May. 31, 2011
7939436 Method of fabricating a semiconductor device May. 10, 2011
7820550 Negative tone double patterning method Oct. 26, 2010
7767100 Patterning method and field effect transistors Aug. 3, 2010
7718081 Techniques for the use of amorphous carbon (APF) for various etch and litho integration schemes May. 18, 2010
7718530 Method for manufacturing semiconductor device May. 18, 2010
7704882 Semiconductor devices using fine patterns and methods of forming fine patterns Apr. 27, 2010
7510951 Method for forming high-resolution pattern with direct writing means Mar. 31, 2009
7265059 Multiple fin formation Sep. 4, 2007
7064078 Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme Jun. 20, 2006
6998348 Method for manufacturing electronic circuits integrated on a semiconductor substrate Feb. 14, 2006
6977203 Method of forming narrow trenches in semiconductor substrates Dec. 20, 2005
6972240 Forming of close thin trenches Dec. 6, 2005
6967140 Quantum wire gate device and method of making same Nov. 22, 2005
6962878 Method to reduce photoresist mask line dimensions Nov. 8, 2005
6960510 Method of making sub-lithographic features Nov. 1, 2005
6893972 Process for sidewall amplification of resist structures and for the production of structures having reduced structure size May. 17, 2005
6855614 Sidewalls as semiconductor etch stop and diffusion barrier Feb. 15, 2005
6841341 Method of depositing an amorphous carbon layer Jan. 11, 2005
6794230 Approach to improve line end shortening Sep. 21, 2004
6740574 Methods of forming DRAM assemblies, transistor devices, and openings in substrates May. 25, 2004
6716570 Low temperature resist trimming process Apr. 6, 2004
6709982 Double spacer FinFET formation Mar. 23, 2004
6580150 Vertical junction field effect semiconductor diodes Jun. 17, 2003
6573030 Method for depositing an amorphous carbon layer Jun. 3, 2003
6500744 Methods of forming DRAM assemblies, transistor devices, and openings in substrates Dec. 31, 2002
6413836 Method of making isolation trench Jul. 2, 2002
6391782 Process for forming multiple active lines and gate-all-around MOSFET May. 21, 2002
6391525 Sidewall patterning for sub 100 nm gate conductors May. 21, 2002
6358800 Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit Mar. 19, 2002
6329124 Method to produce high density memory cells and small spaces by using nitride spacer Dec. 11, 2001
6329227 Method of patterning organic polymer film and method for fabricating semiconductor device Dec. 11, 2001
6228747 Organic sidewall spacers used with resist May. 8, 2001
6210866 Method for forming features using self-trimming by selective etch and device formed thereby Apr. 3, 2001
6183938 Conformal organic coatings for sidewall patterning of sublithographic structures Feb. 6, 2001
6168907 Method for etching semiconductor device Jan. 2, 2001
6121155 Integrated circuit fabrication critical dimension control using self-limiting resist etch Sep. 19, 2000
6030903 Non-destructive method for gauging undercut in a hidden layer Feb. 29, 2000
5935454 Ultrafine fabrication method Aug. 10, 1999
5753524 Method of forming a plateau and a cover on the plateau in particular on a semiconductor substrate May. 19, 1998
5705321 Method for manufacture of quantum sized periodic structures in Si materials Jan. 6, 1998
5675164 High performance multi-mesa field effect transistor Oct. 7, 1997
5665622 Folded trench and rie/deposition process for high-value capacitors Sep. 9, 1997
5328810 Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process Jul. 12, 1994

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