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Class Information
Number: 257/E21.234
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > Chemical or electrical treatment, e.g., electrolytic etching (epo) > Using mask (epo) > Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (epo) > Characterized by their behavior during process, e.g., soluble mask, redeposited mask (epo)
Description: This subclass is indented under subclass E21.233. This subclass is substantially the same in scope as ECLA classification H01L21/308D2.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8358010 Method for realizing a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method Jan. 22, 2013
8349639 Method for manufacturing image sensor Jan. 8, 2013
8288271 Method for reworking antireflective coating over semiconductor substrate Oct. 16, 2012
8278165 Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices Oct. 2, 2012
7977141 Solid-state image pickup device and method of manufacturing the same Jul. 12, 2011
7964907 Integrated circuit device gate structures Jun. 21, 2011
7902006 Method of manufacturing a thin film transistor array substrate Mar. 8, 2011
7018931 Method of forming an isolation film in a semiconductor device Mar. 28, 2006
6972242 Methods to fabricate semiconductor devices Dec. 6, 2005
6960528 Method of forming a nanotip array in a substrate by forming masks on portions of the substrate and etching the unmasked portions Nov. 1, 2005
6919259 Method for STI etching using endpoint detection Jul. 19, 2005
6900141 Method of forming a resist pattern and fabricating tapered features May. 31, 2005
6806037 Method for producing and/or renewing an etching mask Oct. 19, 2004
6709984 Method for manufacturing semiconductor device Mar. 23, 2004
6656341 Method of etching, as well as frame element, mask and prefabricated substrate element for use in such etching Dec. 2, 2003
6583062 Method of improving an aspect ratio while avoiding etch stop Jun. 24, 2003
6458494 Etching method Oct. 1, 2002
6444524 Method for forming a trench capacitor Sep. 3, 2002
6426300 Method for fabricating semiconductor device by using etching polymer Jul. 30, 2002
6391426 High capacitance storage node structures May. 21, 2002
6376300 Process of manufacturing trench capacitor having a hill structure Apr. 23, 2002
6372412 Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby Apr. 16, 2002
6313492 Integrated circuit chip produced by using frequency doubling hybrid photoresist Nov. 6, 2001
6303416 Method to reduce plasma etch fluting Oct. 16, 2001
6299788 Silicon etching process Oct. 9, 2001
6284606 Process to achieve uniform groove depth in a silicon substrate Sep. 4, 2001
6265316 Etching method Jul. 24, 2001
6242363 Method of etching a wafer layer using a sacrificial wall to form vertical sidewall Jun. 5, 2001
6200726 Optimization of space width for hybrid photoresist Mar. 13, 2001
6139647 Selective removal of vertical portions of a film Oct. 31, 2000
6114082 Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same Sep. 5, 2000
5945352 Method for fabrication of shallow isolation trenches with sloped wall profiles Aug. 31, 1999
5776660 Fabrication method for high-capacitance storage node structures Jul. 7, 1998
5767017 Selective removal of vertical portions of a film Jun. 16, 1998
5668023 Composition for off-axis growth sites on non-polar substrates Sep. 16, 1997
5550088 Fabrication process for a self-aligned optical subassembly Aug. 27, 1996
5501893 Method of anisotropically etching silicon Mar. 26, 1996
5443685 Composition and method for off-axis growth sites on nonpolar substrates Aug. 22, 1995
5434447 Semiconductor device having a trench for device isolation and method of fabricating the same Jul. 18, 1995
5382314 Method of shaping a diamond body Jan. 17, 1995
5356823 Method of manufacturing a semiconductor device Oct. 18, 1994
5330617 Method for etching integrated-circuit layers to a fixed depth and corresponding integrated circuit Jul. 19, 1994
5298790 Reactive ion etching buffer mask Mar. 29, 1994
5281550 Method for etching a deep groove in a silicon substrate Jan. 25, 1994
5266518 Method of manufacturing a semiconductor body comprising a mesa Nov. 30, 1993
5240512 Method and structure for forming a trench within a semiconductor layer of material Aug. 31, 1993
5139964 Method for forming isolation region of semiconductor device Aug. 18, 1992
5131978 Low temperature, single side, multiple step etching process for fabrication of small and large structures Jul. 21, 1992
5120675 Method for forming a trench within a semiconductor layer of material Jun. 9, 1992

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