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Class Information
Number: 257/E21.197
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (epo) > Making electrode structure comprising conductor-insulator-semiconductor, e.g., mis gate (epo) > Insulator formed on silicon semiconductor body (epo) > Characterized by conductor (epo) > Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (epo)
Description: This subclass is indented under subclass E21.195. This subclass is substantially the same in scope as ECLA classification H01L21/28E2B2.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.198 Conductor comprising at least another nonsilicon conductive layer (epo) 87

Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
8685826 Method for manufacturing nano-crystalline silicon material from chloride chemistries for the semiconductor integrated circuits Apr. 1, 2014
8551837 Methods of fabricating high-K metal gate devices Oct. 8, 2013
8546249 Selective growth of polycrystalline silicon-containing semiconductor material on a silicon-containing semiconductor surface Oct. 1, 2013
8471338 Dual polysilicon gate of a semiconductor device with a multi-plane channel Jun. 25, 2013
8450813 Fin transistor structure and method of fabricating the same May. 28, 2013
8445973 Fin transistor structure and method of fabricating the same May. 21, 2013
8410554 Method, structure and design structure for customizing history effects of SOI circuits Apr. 2, 2013
8237221 Semiconductor device and method of manufacturing semiconductor device Aug. 7, 2012
8193051 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics Jun. 5, 2012
7989362 Hafnium lanthanide oxynitride films Aug. 2, 2011
7964514 Multiple nitrogen plasma treatments for thin SiON dielectrics Jun. 21, 2011
7892961 Methods for forming MOS devices with metal-inserted polysilicon gate stack Feb. 22, 2011
7875518 Semiconductor device having silicon layer in a gate electrode Jan. 25, 2011
7858479 Method and apparatus of fabricating semiconductor device Dec. 28, 2010
7842579 Method for manufacturing a semiconductor device having doped and undoped polysilicon layers Nov. 30, 2010
7808014 Semiconductor device having insulated gate bipolar transistor Oct. 5, 2010
7737505 Semiconductor device and method of forming the same Jun. 15, 2010
7714366 CMOS transistor with a polysilicon gate electrode having varying grain size May. 11, 2010
7704823 Strained semiconductor device and method of making same Apr. 27, 2010
7629219 Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel Dec. 8, 2009
7622383 Methods of forming conductive polysilicon thin films via atomic layer deposition and methods of manufacturing semiconductor devices including such polysilicon thin films Nov. 24, 2009
7592240 Method for forming a gate structure through an amorphous silicon layer and applications thereof Sep. 22, 2009
7563730 Hafnium lanthanide oxynitride films Jul. 21, 2009
7547621 LPCVD gate hard mask Jun. 16, 2009
7544604 Tantalum lanthanide oxynitride films Jun. 9, 2009
7538001 Transistor gate forming methods and integrated circuits May. 26, 2009
7476600 FET gate structure and fabrication process Jan. 13, 2009
7476627 Surface preparation prior to deposition Jan. 13, 2009
7365027 ALD of amorphous lanthanide doped TiO.sub.x films Apr. 29, 2008
7224026 Nanoelectronic devices and circuits May. 29, 2007
7074684 Elevated source drain disposable spacer CMOS Jul. 11, 2006
7056835 Surface preparation prior to deposition Jun. 6, 2006
7026218 Use of indium to define work function of p-type doped polysilicon Apr. 11, 2006
7015121 Semiconductor device and method of manufacturing the same Mar. 21, 2006
7008876 Method of forming gate electrode structure of a semiconductor device Mar. 7, 2006
6991999 Bi-layer silicon film and method of fabrication Jan. 31, 2006
6982215 N type impurity doping using implantation of P.sub.2+ ions or As.sub.2+ Ions Jan. 3, 2006
6967384 Structure and method for ultra-small grain size polysilicon Nov. 22, 2005
6958277 Surface preparation prior to deposition Oct. 25, 2005
6936518 Creating shallow junction transistors Aug. 30, 2005
6929991 Reliable semiconductor device and method of manufacturing the same Aug. 16, 2005
6911384 Gate structure with independently tailored vertical doping profile Jun. 28, 2005
6900115 Deposition over mixed substrates May. 31, 2005
6893948 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size May. 17, 2005
6875676 Methods for producing a highly doped electrode for a field effect transistor Apr. 5, 2005
6867080 Polysilicon tilting to prevent geometry effects during laser thermal annealing Mar. 15, 2005
6858903 MOSFET device with in-situ doped, raised source and drain structures Feb. 22, 2005
6855567 Etch endpoint detection Feb. 15, 2005
6855643 Method for fabricating a gate structure Feb. 15, 2005
6849487 Method for forming an electronic structure using etch Feb. 1, 2005

1 2 3 4 5 6

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