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Class Information
Number: 257/E21.195
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (epo) > Making electrode structure comprising conductor-insulator-semiconductor, e.g., mis gate (epo) > Insulator formed on silicon semiconductor body (epo) > Characterized by conductor (epo)
Description: This subclass is indented under subclass E21.191. This subclass is substantially the same in scope as ECLA classification H01L21/28E2B.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.205 Characterized by sectional shape, e.g., t-shape, inverted t, spacer (epo) 441
257/E21.203 Conductor layer next to insulator is metallic silicide (me si) (epo) 110
257/E21.204 Conductor layer next to insulator is non-mesi composite or compound, e.g., tin (epo) 146
257/E21.201 Conductor layer next to insulator is si or ge or c and their non-si alloys (epo) 125
257/E21.202 Conductor layer next to the insulator is single metal, e.g., ta, w, mo, al (epo) 157
257/E21.197 Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (epo) 267
257/E21.196 Final conductor next to insulator having lateral composition or doping variation, or being formed laterally by more than one deposition step (epo) 114
257/E21.206 Lithography, isolation, or planarization-related aspects of making conductor-insulator-semiconductor structure, e.g., sub-lithography lengths; to solve problems arising at crossing with side of device isolation (epo) 490


Patents under this class:

Patent Number Title Of Patent Date Issued
8546892 Semiconductor device and method for manufacturing semiconductor device Oct. 1, 2013
7968956 Semiconductor device Jun. 28, 2011
7943442 SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device May. 17, 2011
7892961 Methods for forming MOS devices with metal-inserted polysilicon gate stack Feb. 22, 2011
7855134 Semiconductor device and manufacturing method of the same Dec. 21, 2010
7579277 Semiconductor device and method for fabricating the same Aug. 25, 2009
7199043 Method of forming copper wiring in semiconductor device Apr. 3, 2007
7129170 Method for depositing and etching ruthenium layers Oct. 31, 2006
6797641 Gate oxide stabilization by means of germanium components in gate conductor Sep. 28, 2004
6461878 Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode Oct. 8, 2002
6441464 Gate oxide stabilization by means of germanium components in gate conductor Aug. 27, 2002
6284609 Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions Sep. 4, 2001
6281532 Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering Aug. 28, 2001
5885889 Process of fabricating semiconductor device having doped polysilicon layer without segregation of dopant impurity Mar. 23, 1999
5843827 Method of reducing dielectric damage from plasma etch charging Dec. 1, 1998
5801399 Semiconductor device with antireflection film Sep. 1, 1998
5512497 Method of manufacturing a semiconductor integrated circuit device Apr. 30, 1996
5413966 Shallow trench etch May. 9, 1995
5362356 Plasma etching process control Nov. 8, 1994
5354699 Method of manufacturing semiconductor integrated circuit device Oct. 11, 1994
5328864 Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions Jul. 12, 1994
4737474 Silicide to silicon bonding process Apr. 12, 1988











 
 
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