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Class Information
Number: 257/E21.184
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (epo) > Manufacture or post-treatment of electrode having a capacitive structure, i.e., gate structure for field-effect device (epo) > Pn-homojunction gate structure (epo)
Description: This subclass is indented under subclass E21.176. This subclass is substantially the same in scope as ECLA classification H01L21/28B3.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.185 For charge-coupled device (epo) 21

Patents under this class:

Patent Number Title Of Patent Date Issued
8216888 Eliminating poly uni-direction line-end shortening using second cut Jul. 10, 2012
7939384 Eliminating poly uni-direction line-end shortening using second cut May. 10, 2011

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