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Class Information
Number: 257/E21.15
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Diffusion of impurity material, e.g., doping material, electrode material, into or out of a semiconductor body, or between semiconductor regions; interactions between two or more impurities; redistribution of impurities (epo) > Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (epo) > Diffusion into or out of group iv semiconductor (epo) > From or through or into an applied layer, e.g., photoresist, nitride (epo) > Applied layer is oxide, e.g., p 2 o 5 , psg, h 3 bo 3 , doped oxide (epo) > Through the applied layer (epo)
Description: This subclass is indented under subclass E21.149. This subclass is substantially the same in scope as ECLA classification H01L21/225A4D2.

Patents under this class:

Patent Number Title Of Patent Date Issued
8563409 Film-forming composition Oct. 22, 2013
8530944 Semiconductor device Sep. 10, 2013
8114695 Solid-state image pickup element, solid-state image pickup device and production method therefor Feb. 14, 2012
7935618 Sputtering-less ultra-low energy ion implantation May. 3, 2011
7598159 Method of fabricating thin film transistor substrate and thin film transistor substrate produced using the same Oct. 6, 2009
7303967 Method for fabricating transistor of semiconductor device Dec. 4, 2007
7148109 Method for manufacturing flash memory device Dec. 12, 2006
7112539 Dielectric layer for semiconductor device and method of manufacturing the same Sep. 26, 2006
7087503 Shallow self isolated doped implanted silicon process Aug. 8, 2006
7019342 Double-gated transistor circuit Mar. 28, 2006
7015547 Multi-configurable independently multi-gated MOSFET Mar. 21, 2006
6946364 Integrated circuit having a device wafer with a diffused doped backside layer Sep. 20, 2005
6919647 SRAM cell Jul. 19, 2005
6867495 Integrated circuit having a device wafer with a diffused doped backside layer Mar. 15, 2005
6642121 Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition Nov. 4, 2003
6624049 Semiconductor device and method of manufacturing the same Sep. 23, 2003
6498079 Method for selective source diffusion Dec. 24, 2002
6448105 Method for doping one side of a semiconductor body Sep. 10, 2002
6372588 Method of making an IGFET using solid phase diffusion to dope the gate, source and drain Apr. 16, 2002
6362075 Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide Mar. 26, 2002
6197983 Germanes and doping with germanes Mar. 6, 2001
6133119 Photoelectric conversion device and method manufacturing same Oct. 17, 2000
6133126 Method for fabricating a dopant region Oct. 17, 2000
6008096 Ultra short transistor fabrication method Dec. 28, 1999
5998271 Method of producing an MOS transistor Dec. 7, 1999
5969398 Method for producing a semiconductor device and a semiconductor device Oct. 19, 1999
5946580 Method to form elevated source/drain with solid phase diffused source/drain extension for MOSFET Aug. 31, 1999
5918129 Method of channel doping using diffusion from implanted polysilicon Jun. 29, 1999
5736446 Method of fabricating a MOS device having a gate-side air-gap structure Apr. 7, 1998
5710054 Method of forming a shallow junction by diffusion from a silicon-based spacer Jan. 20, 1998
5661059 Boron penetration to suppress short channel effect in P-channel device Aug. 26, 1997
5633522 CMOS transistor with two-layer inverse-T tungsten gate May. 27, 1997
5599725 Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure Feb. 4, 1997
5479047 Self-aligned bipolar transistor with very thin dielectric layer interfacing between poly and active area Dec. 26, 1995
5407847 Method for fabricating a semiconductor device having a shallow doped region Apr. 18, 1995
5374481 Polyemitter structure with improved interface control Dec. 20, 1994
5354710 Method of manufacturing semiconductor devices using an adsorption enhancement layer Oct. 11, 1994
5279976 Method for fabricating a semiconductor device having a shallow doped region Jan. 18, 1994
5194397 Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface Mar. 16, 1993
5153146 Maufacturing method of semiconductor devices Oct. 6, 1992
5141895 Semiconductor device process using diffusant penetration and source layers for shallow regions Aug. 25, 1992
4755487 Method for making bipolar transistors using rapid thermal annealing Jul. 5, 1988
4604150 Controlled boron doping of silicon Aug. 5, 1986
4451303 Diffusion of aluminum May. 29, 1984
4332076 Method of manufacturing a semiconductor device Jun. 1, 1982
4151006 Method of manufacturing a semiconductor device Apr. 24, 1979
4003071 Method of manufacturing an insulated gate field effect transistor Jan. 11, 1977

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