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Class Information
Number: 257/E21.129
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Deposition of semiconductor material on substrate, e.g., epitaxial growth, solid phase epitaxy (epo) > Characterized by the substrate (epo) > Group iva, e.g., si, c, ge on group ivb, e.g., ti, zr (epo)
Description: This subclass is indented under subclass E21.124. This subclass is substantially the same in scope as ECLA classification H01L21/20B6B8.

Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8709957 Spalling utilizing stressor layer portions Apr. 29, 2014
8686489 Memory with metal-insulator-metal tunneling program and erase Apr. 1, 2014
8652963 MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture Feb. 18, 2014
8609548 Method for providing high etch rate Dec. 17, 2013
8557688 Method for fabricating P-type polycrystalline silicon-germanium structure Oct. 15, 2013
8551889 Manufacture method for photovoltaic module Oct. 8, 2013
8507952 Semiconductor wafer, semiconductor device, and method for producing semiconductor wafer Aug. 13, 2013
8481410 Methods of epitaxial FinFET Jul. 9, 2013
8187982 Manufacture method for photovoltaic module May. 29, 2012
8168971 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain May. 1, 2012
8110880 Systems and methods for interconnect metallization using a stop-etch layer Feb. 7, 2012
8058143 Substrate bonding with metal germanium silicon material Nov. 15, 2011
8043914 Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate Oct. 25, 2011
8003510 Fabrication methods for nano-scale chalcopyritic powders and polymeric thin-film solar cells Aug. 23, 2011
7998877 Diffraction grating in conjunction with reduced thickness to increase efficiency of solar cells Aug. 16, 2011
7968438 Ultra-thin high-quality germanium on silicon by low-temperature epitaxy and insulator-capped annealing Jun. 28, 2011
7932184 Method of manufacturing solar cell module and solar cell module thus manufactured Apr. 26, 2011
7932534 High light extraction efficiency solid state light sources Apr. 26, 2011
7906439 Method of fabricating a MEMS/NEMS electromechanical component Mar. 15, 2011
7897480 Preparation of high quality strained-semiconductor directly-on-insulator substrates Mar. 1, 2011
7867836 Method for manufacturing junction semiconductor device Jan. 11, 2011
7855125 Method for manufacturing semiconductor device and semiconductor device Dec. 21, 2010
7829460 Method of manufracturing increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride Nov. 9, 2010
7825020 Method for manufacturing semiconductor device Nov. 2, 2010
7785995 Semiconductor buffer structures Aug. 31, 2010
7704815 Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques Apr. 27, 2010
7608865 Club extension to a T-gate high electron mobility transistor Oct. 27, 2009
7494902 Method of fabricating a strained multi-gate transistor Feb. 24, 2009
7488670 Direct channel stress Feb. 10, 2009
7473587 High-quality SGOI by oxidation near the alloy melting temperature Jan. 6, 2009
7459718 Field effect transistor Dec. 2, 2008
7452757 Silicon-on-insulator structures and methods Nov. 18, 2008
7427811 Semiconductor substrate Sep. 23, 2008
7410917 Atomic layer deposited Zr-Sn-Ti-O films using TiI.sub.4 Aug. 12, 2008
7371637 Oxide-nitride stack gate dielectric May. 13, 2008
7364980 Manufacturing method of semiconductor substrate Apr. 29, 2008
7348260 Method for forming a relaxed or pseudo-relaxed useful layer on a substrate Mar. 25, 2008
7332443 Method for fabricating a semiconductor device Feb. 19, 2008
7271436 Flash memory devices including a pass transistor Sep. 18, 2007
7256142 Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits Aug. 14, 2007
7241670 Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen Jul. 10, 2007
7229876 Method of fabricating memory Jun. 12, 2007
7223662 Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface May. 29, 2007
7217668 Gate technology for strained surface channel and strained buried channel MOSFET devices May. 15, 2007
7138309 Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer Nov. 21, 2006
7122483 Gate technology for strained surface channel and strained buried channel MOSFET devices Oct. 17, 2006
7074686 Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications Jul. 11, 2006
7071014 Methods for preserving strained semiconductor substrate layers during CMOS processing Jul. 4, 2006
7060597 Manufacturing method for a silicon substrate having strained layer Jun. 13, 2006
7049627 Semiconductor heterostructures and related methods May. 23, 2006

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