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Class Information
Number: 257/E21.103
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Deposition of semiconductor material on substrate, e.g., epitaxial growth, solid phase epitaxy (epo) > Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (epo) > Epitaxial deposition of group iv elements, e.g., si, ge, c (epo) > Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (epo)
Description: This subclass is indented under subclass E21.102. This subclass is substantially the same in scope as ECLA classification H01L21/205B2.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7439567 |
Contactless nonvolatile memory array |
Oct. 21, 2008 |
| 7429766 |
Split gate type nonvolatile memory device |
Sep. 30, 2008 |
| 7399686 |
Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate |
Jul. 15, 2008 |
| 7365383 |
Method of forming an EPROM cell and structure therefor |
Apr. 29, 2008 |
| 7341929 |
Method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control |
Mar. 11, 2008 |
| 7339226 |
Dual-level stacked flash memory cell with a MOSFET storage transistor |
Mar. 4, 2008 |
| 7332399 |
Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled |
Feb. 19, 2008 |
| 7312136 |
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
Dec. 25, 2007 |
| 7294883 |
Nonvolatile memory cells with buried channel transistors |
Nov. 13, 2007 |
| 7262117 |
Germanium integrated CMOS wafer and method for manufacturing the same |
Aug. 28, 2007 |
| 7229901 |
Fabrication of strained heterojunction structures |
Jun. 12, 2007 |
| 7060597 |
Manufacturing method for a silicon substrate having strained layer |
Jun. 13, 2006 |
| 7056789 |
Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor |
Jun. 6, 2006 |
| 7041170 |
Method of producing high quality relaxed silicon germanium layers |
May. 9, 2006 |
| 6982208 |
Method for producing high throughput strained-Si channel MOSFETS |
Jan. 3, 2006 |
| 6946373 |
Relaxed, low-defect SGOI for strained Si CMOS applications |
Sep. 20, 2005 |
| 6878610 |
Relaxed silicon germanium substrate with low defect density |
Apr. 12, 2005 |
| 6723622 |
Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer |
Apr. 20, 2004 |
| 6228166 |
Method for boron contamination reduction in IC fabrication |
May. 8, 2001 |
| 6117750 |
Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively |
Sep. 12, 2000 |
| 5670414 |
Graded-gap process for growing a SiC/Si heterojunction structure |
Sep. 23, 1997 |
| 5523160 |
Highly-oriented diamond film |
Jun. 4, 1996 |
| 5256550 |
Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x layer |
Oct. 26, 1993 |
| 5091333 |
Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth |
Feb. 25, 1992 |
| 5084411 |
Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film |
Jan. 28, 1992 |
| 4885614 |
Semiconductor device with crystalline silicon-germanium-carbon alloy |
Dec. 5, 1989 |
| 4843030 |
Semiconductor processing by a combination of photolytic, pyrolytic and catalytic processes |
Jun. 27, 1989 |
| 4632712 |
Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth |
Dec. 30, 1986 |
| 4357183 |
Heteroepitaxy of germanium silicon on silicon utilizing alloying control |
Nov. 2, 1982 |
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