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Class Information
Number: 257/E21.048
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising carbon, e.g., diamond, diamond-like carbon (epo) > Making electrode (epo) > Conductor-insulator-semiconductor electrode, e.g., mis contacts (epo)
Description: This subclass is indented under subclass E21.045. This subclass is substantially the same in scope as ECLA classification H01L21/04D20E.


Patents under this class:

Patent Number Title Of Patent Date Issued
7456063 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method Nov. 25, 2008
7259426 Semiconductor device and its manufacturing method Aug. 21, 2007
7217616 Non-volatile memory cell and method of forming the same May. 15, 2007
6180519 Method of forming a layered wiring structure including titanium silicide Jan. 30, 2001
5801425 Semiconductor device having a wiring layer including a TISI2, film of the C49 or C54 structure Sep. 1, 1998
5350944 Insulator films on diamonds Sep. 27, 1994
5196907 Metal insulator semiconductor field effect transistor Mar. 23, 1993



 
 
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