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Class Information
Number: 257/E21.039
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Making mask on semicond uctor body for further photolithographic processing (epo) > Comprising inorganic layer (epo) > Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (epo) > Process specially adapted to improve the resolution of the mask (epo)
Description: This subclass is indented under subclass E21.036. This subclass is substantially the same in scope as ECLA classification H01L21/033F6.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7396781 |
Method and apparatus for adjusting feature size and position |
Jul. 8, 2008 |
| 7381654 |
Method for fabricating right-angle holes in a substrate |
Jun. 3, 2008 |
| 7361588 |
Etch process for CD reduction of arc material |
Apr. 22, 2008 |
| 7351666 |
Layout and process to contact sub-lithographic structures |
Apr. 1, 2008 |
| 7316978 |
Method for forming recesses |
Jan. 8, 2008 |
| 7314824 |
Nitrogen-free ARC/capping layer and method of manufacturing the same |
Jan. 1, 2008 |
| 7179748 |
Method for forming recesses |
Feb. 20, 2007 |
| 7064078 |
Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
Jun. 20, 2006 |
| 7052972 |
Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
May. 30, 2006 |
| 7033948 |
Method for reducing dimensions between patterns on a photoresist |
Apr. 25, 2006 |
| 7030008 |
Techniques for patterning features in semiconductor devices |
Apr. 18, 2006 |
| 7026247 |
Nanocircuit and self-correcting etching method for fabricating same |
Apr. 11, 2006 |
| 7001710 |
Method for forming ultra fine contact holes in semiconductor devices |
Feb. 21, 2006 |
| 6998348 |
Method for manufacturing electronic circuits integrated on a semiconductor substrate |
Feb. 14, 2006 |
| 6972255 |
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
Dec. 6, 2005 |
| 6962878 |
Method to reduce photoresist mask line dimensions |
Nov. 8, 2005 |
| 6960510 |
Method of making sub-lithographic features |
Nov. 1, 2005 |
| 6946400 |
Patterning method for fabricating integrated circuit |
Sep. 20, 2005 |
| 6942732 |
Method for forming double density wordline |
Sep. 13, 2005 |
| 6936383 |
Method of defining the dimensions of circuit elements by using spacer deposition techniques |
Aug. 30, 2005 |
| 6924191 |
Method for fabricating a gate structure of a field effect transistor |
Aug. 2, 2005 |
| 6884727 |
Semiconductor fabrication process for modifying the profiles of patterned features |
Apr. 26, 2005 |
| 6875703 |
Method for forming quadruple density sidewall image transfer (SIT) structures |
Apr. 5, 2005 |
| 6875689 |
Method of patterning lines in semiconductor devices |
Apr. 5, 2005 |
| 6864184 |
Method for reducing critical dimension attainable via the use of an organic conforming layer |
Mar. 8, 2005 |
| 6864041 |
Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching |
Mar. 8, 2005 |
| 6835662 |
Partially de-coupled core and periphery gate module process |
Dec. 28, 2004 |
| 6828237 |
Sidewall polymer deposition method for forming a patterned microelectronic layer |
Dec. 7, 2004 |
| 6828082 |
Method to pattern small features by using a re-flowable hard mask |
Dec. 7, 2004 |
| 6818519 |
Method of forming organic spacers and using organic spacers to form semiconductor device features |
Nov. 16, 2004 |
| 6794230 |
Approach to improve line end shortening |
Sep. 21, 2004 |
| 6774051 |
Method for reducing pitch |
Aug. 10, 2004 |
| 6764947 |
Method for reducing gate line deformation and reducing gate line widths in semiconductor devices |
Jul. 20, 2004 |
| 6762130 |
Method of photolithographically forming extremely narrow transistor gate elements |
Jul. 13, 2004 |
| 6759180 |
Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography |
Jul. 6, 2004 |
| 6756284 |
Method for forming a sublithographic opening in a semiconductor process |
Jun. 29, 2004 |
| 6753266 |
Method of enhancing gate patterning properties with reflective hard mask |
Jun. 22, 2004 |
| 6750150 |
Method for reducing dimensions between patterns on a photoresist |
Jun. 15, 2004 |
| 6743712 |
Method of making a semiconductor device by forming a masking layer with a tapered etch profile |
Jun. 1, 2004 |
| 6734107 |
Pitch reduction in semiconductor fabrication |
May. 11, 2004 |
| 6713348 |
Method for forming an etch mask during the manufacture of a semiconductor device |
Mar. 30, 2004 |
| 6699792 |
Polymer spacers for creating small geometry space and method of manufacture thereof |
Mar. 2, 2004 |
| 6689695 |
Multi-purpose composite mask for dual damascene patterning |
Feb. 10, 2004 |
| 6670277 |
Method of manufacturing semiconductor device |
Dec. 30, 2003 |
| 6667237 |
Method and apparatus for patterning fine dimensions |
Dec. 23, 2003 |
| 6664191 |
Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space |
Dec. 16, 2003 |
| 6653058 |
Methods for reducing profile variation in photoresist trimming |
Nov. 25, 2003 |
| 6642152 |
Method for ultra thin resist linewidth reduction using implantation |
Nov. 4, 2003 |
| 6638441 |
Method for pitch reduction |
Oct. 28, 2003 |
| 6620715 |
Method for forming sub-critical dimension structures in an integrated circuit |
Sep. 16, 2003 |
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