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Class Information
Number: 257/E21.037
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Making mask on semicond uctor body for further photolithographic processing (epo) > Comprising inorganic layer (epo) > Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (epo) > Characterized by their behavior during process, e.g., soluble mask, re-deposited mask (epo)
Description: This subclass is indented under subclass E21.036. This subclass is substantially the same in scope as ECLA classification H01L21/033F2.


Patents under this class:

Patent Number Title Of Patent Date Issued
7309659 Silicon-containing resist to pattern organic low k-dielectrics Dec. 18, 2007
7297559 Method of fabricating memory and memory Nov. 20, 2007
7033948 Method for reducing dimensions between patterns on a photoresist Apr. 25, 2006
7018931 Method of forming an isolation film in a semiconductor device Mar. 28, 2006
6919259 Method for STI etching using endpoint detection Jul. 19, 2005
6864188 Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask Mar. 8, 2005
6852637 Method of etching a mask layer and a protecting layer for metal contact windows Feb. 8, 2005
6750150 Method for reducing dimensions between patterns on a photoresist Jun. 15, 2004
6730609 Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device May. 4, 2004
6653058 Methods for reducing profile variation in photoresist trimming Nov. 25, 2003
6573188 End point detection method for forming a patterned silicon layer Jun. 3, 2003
6458494 Etching method Oct. 1, 2002
6426300 Method for fabricating semiconductor device by using etching polymer Jul. 30, 2002
6387774 Methods for forming patterned layers including notched etching masks May. 14, 2002
6319822 Process for forming an integrated contact or via Nov. 20, 2001
6316169 Methods for reducing profile variation in photoresist trimming Nov. 13, 2001
6265317 Top corner rounding for shallow trench isolation Jul. 24, 2001
6258732 Method of forming a patterned organic dielectric layer on a substrate Jul. 10, 2001
6210595 Method for producing structures having a high aspect ratio and structure having a high aspect ratio Apr. 3, 2001
6139647 Selective removal of vertical portions of a film Oct. 31, 2000
5877071 Masking methods during semiconductor device fabrication Mar. 2, 1999
5767017 Selective removal of vertical portions of a film Jun. 16, 1998
5759880 Resistless methods of fabricating FETs Jun. 2, 1998
5670062 Method for producing tapered lines Sep. 23, 1997
5472895 Method for manufacturing a transistor of a semiconductor device Dec. 5, 1995
5330617 Method for etching integrated-circuit layers to a fixed depth and corresponding integrated circuit Jul. 19, 1994
4889828 Process for the production of electrical isolation zones in a CMOS integrated circuit Dec. 26, 1989
4597826 Method for forming patterns Jul. 1, 1986
4577394 Reduction of field oxide encroachment in MOS fabrication Mar. 25, 1986
4352724 Method of manufacturing a semiconductor device Oct. 5, 1982
4092210 Process for the production of etched structures in a surface of a solid body by ionic etching May. 30, 1978



 
 
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