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Class Information
Number: 257/E21.033
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Making mask on semicond uctor body for further photolithographic processing (epo) > Comprising inorganic layer (epo)
Description: This subclass is indented under subclass E21.023. This subclass is substantially the same in scope as ECLA classification H01L21/033.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7432212 |
Methods of processing a semiconductor substrate |
Oct. 7, 2008 |
| 7416995 |
Method for fabricating controlled stress silicon nitride films |
Aug. 26, 2008 |
| 7393707 |
Method for manufacturing an electro-optical device |
Jul. 1, 2008 |
| 7329613 |
Structure and method for forming semiconductor wiring levels using atomic layer deposition |
Feb. 12, 2008 |
| 7288420 |
Method for manufacturing an electro-optical device |
Oct. 30, 2007 |
| 7241688 |
Aperture masks for circuit fabrication |
Jul. 10, 2007 |
| 7192789 |
Method for monitoring an ion implanter |
Mar. 20, 2007 |
| 7176053 |
Laser ablation method for fabricating high performance organic devices |
Feb. 13, 2007 |
| 7172965 |
Method for manufacturing semiconductor device |
Feb. 6, 2007 |
| 7138341 |
Process for making a memory structure |
Nov. 21, 2006 |
| 7115524 |
Methods of processing a semiconductor substrate |
Oct. 3, 2006 |
| 6797597 |
Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process |
Sep. 28, 2004 |
| 6743729 |
Etching method and etching apparatus of carbon thin film |
Jun. 1, 2004 |
| 6225217 |
Method of manufacturing semiconductor device having multilayer wiring |
May. 1, 2001 |
| 6140225 |
Method of manufacturing semiconductor device having multilayer wiring |
Oct. 31, 2000 |
| 6025268 |
Method of etching conductive lines through an etch resistant photoresist mask |
Feb. 15, 2000 |
| 6025115 |
Processing method for etching a substrate |
Feb. 15, 2000 |
| 5981001 |
Processing method for selectively irradiating a surface in presence of a reactive gas to cause etching |
Nov. 9, 1999 |
| 5962194 |
Processing method and apparatus |
Oct. 5, 1999 |
| 5863706 |
Processing method for patterning a film |
Jan. 26, 1999 |
| 5847465 |
Contacts for semiconductor devices |
Dec. 8, 1998 |
| 5837560 |
Method of masking substrates leaving exposed facets |
Nov. 17, 1998 |
| 5824455 |
Processing method and apparatus |
Oct. 20, 1998 |
| 5714306 |
Processing method and apparatus |
Feb. 3, 1998 |
| 5528058 |
IGBT device with platinum lifetime control and reduced gaw |
Jun. 18, 1996 |
| 5420067 |
Method of fabricatring sub-half-micron trenches and holes |
May. 30, 1995 |
| 5409566 |
Slope etching process |
Apr. 25, 1995 |
| 5334550 |
Method of producing a self-aligned window at recessed intersection of insulating regions |
Aug. 2, 1994 |
| 5283201 |
High density power device fabrication process |
Feb. 1, 1994 |
| 5283202 |
IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions |
Feb. 1, 1994 |
| 5262336 |
IGBT process to produce platinum lifetime control |
Nov. 16, 1993 |
| 5256583 |
Mask surrogate semiconductor process with polysilicon gate protection |
Oct. 26, 1993 |
| 5246879 |
Method of forming nanometer-scale trenches and holes |
Sep. 21, 1993 |
| 5212103 |
Method of making a heterojunction bipolar transistor |
May. 18, 1993 |
| 5204276 |
Method of manufacturing semiconductor device |
Apr. 20, 1993 |
| 5182234 |
Profile tailored trench etch using a SF.sub.6 -O.sub.2 etching composition wherein both isotropic and anisotropic etching is achieved by varying the amount of oxygen |
Jan. 26, 1993 |
| 5127989 |
Method of forming a thin film pattern with a trapezoidal cross section |
Jul. 7, 1992 |
| 5119150 |
Compound semiconductor structure including layer limiting silicon diffusion |
Jun. 2, 1992 |
| 5110760 |
Method of nanometer lithography |
May. 5, 1992 |
| 5100813 |
Method of manufacturing bipolar transistor |
Mar. 31, 1992 |
| 5089434 |
Mask surrogate semiconductor process employing dopant-opaque region |
Feb. 18, 1992 |
| 5079177 |
Process for fabricating high performance BiCMOS circuits |
Jan. 7, 1992 |
| 5073812 |
Heterojunction bipolar transistor |
Dec. 17, 1991 |
| 5070029 |
Semiconductor process using selective deposition |
Dec. 3, 1991 |
| 5067002 |
Integrated circuit structures having polycrystalline electrode contacts |
Nov. 19, 1991 |
| 5064774 |
Self-aligned bipolar transistor process |
Nov. 12, 1991 |
| 5061645 |
Method of manufacturing a bipolar transistor |
Oct. 29, 1991 |
| 5049964 |
Bipolar transistor and method of manufacturing the same |
Sep. 17, 1991 |
| 5047366 |
Method of diffusing silicon into compound semiconductors and compound semiconductor devices |
Sep. 10, 1991 |
| 5034351 |
Process for forming a feature on a substrate without recessing the surface of the substrate |
Jul. 23, 1991 |
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