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Class Information
Number: 257/920
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Conductor layers on different levels connected in parallel (e.g., to reduce resistance)
Description: Subject matter wherein a device contains layers of electrical conductors and different conductor layers are electrically connected in parallel, to improve device operation (e.g., to reduce conductor resistance).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7339230 |
Structure and method for making high density mosfet circuits with different height contact lines |
Mar. 4, 2008 |
| 7170175 |
Semiconductor device and production method thereof |
Jan. 30, 2007 |
| 6949839 |
Aligned buried structures formed by surface transformation of empty spaces in solid state materials |
Sep. 27, 2005 |
| 6885078 |
Circuit isolation utilizing MeV implantation |
Apr. 26, 2005 |
| 6885044 |
Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates |
Apr. 26, 2005 |
| 6861705 |
Driver circuits and methods for manufacturing driver circuits |
Mar. 1, 2005 |
| 6844629 |
Display panel with bypassing lines |
Jan. 18, 2005 |
| 6841408 |
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials |
Jan. 11, 2005 |
| 6822329 |
Integrated circuit connecting pad |
Nov. 23, 2004 |
| 6579738 |
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials |
Jun. 17, 2003 |
| 6531755 |
Semiconductor device and manufacturing method thereof for realizing high packaging density |
Mar. 11, 2003 |
| 6498384 |
Structure and method of semiconductor via testing |
Dec. 24, 2002 |
| 6492736 |
Power mesh bridge |
Dec. 10, 2002 |
| 6469360 |
Integrated circuit devices providing reduced electric fields during fabrication thereof |
Oct. 22, 2002 |
| 6455885 |
Inductor structure for high performance system-on-chip using post passivation process |
Sep. 24, 2002 |
| 6348723 |
Semiconductor device with a dummy wire positioned to prevent charging/discharging of the parasitic capacitance of a signal wire |
Feb. 19, 2002 |
| 6320262 |
Semiconductor device and manufacturing method thereof |
Nov. 20, 2001 |
| 6303983 |
Apparatus for manufacturing resin-encapsulated semiconductor devices |
Oct. 16, 2001 |
| 6215077 |
Thin-film laminate type conductor |
Apr. 10, 2001 |
| 6177716 |
Low loss capacitor structure |
Jan. 23, 2001 |
| 6114767 |
EEPROM semiconductor device and method of fabricating the same |
Sep. 5, 2000 |
| 6020612 |
Semiconductor integrated circuit having efficient layout of wiring lines |
Feb. 1, 2000 |
| 5945717 |
Segmented non-volatile memory array having multiple sources |
Aug. 31, 1999 |
| 5854515 |
Integrated circuit having conductors of enhanced cross-sectional area |
Dec. 29, 1998 |
| 5838032 |
Precision capacitor array |
Nov. 17, 1998 |
| 5789791 |
Multi-finger MOS transistor with reduced gate resistance |
Aug. 4, 1998 |
| 5760476 |
Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure |
Jun. 2, 1998 |
| 5635767 |
Semiconductor device having built-in high frequency bypass capacitor |
Jun. 3, 1997 |
| 5600168 |
Semiconductor element and method for fabricating the same |
Feb. 4, 1997 |
| 5594281 |
Semiconductor apparatus having wiring structure of an integrated circuit in which a plurality of logic circuits of the same structure are arranged in the same direction |
Jan. 14, 1997 |
| 5559345 |
Thin film transistor having redundant metal patterns |
Sep. 24, 1996 |
| 5528082 |
Thin-film structure with tapered feature |
Jun. 18, 1996 |
| 5491352 |
Semiconductor device having peripheral metal wiring |
Feb. 13, 1996 |
| 5477085 |
Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits |
Dec. 19, 1995 |
| 5461260 |
Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density |
Oct. 24, 1995 |
| 5455456 |
Integrated circuit package lid |
Oct. 3, 1995 |
| 5391920 |
Semiconductor device having peripheral metal wiring |
Feb. 21, 1995 |
| 5309015 |
Clock wiring and semiconductor integrated circuit device having the same |
May. 3, 1994 |
| 5300814 |
Semiconductor device having a semiconductor substrate with reduced step between memory cells |
Apr. 5, 1994 |
| 5274264 |
Defect tolerant power distribution network and method for integrated circuits |
Dec. 28, 1993 |
| 5184321 |
Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement |
Feb. 2, 1993 |
| 5166759 |
Semiconductor-type laminated ceramic capacitor with a grain boundary-insulated structure |
Nov. 24, 1992 |
| 4961053 |
Circuit arrangement for testing integrated circuit components |
Oct. 2, 1990 |
| 4924111 |
Microprocessor layout minimizing temperature and current effects |
May. 8, 1990 |
| 4845539 |
Semiconductor memory device |
Jul. 4, 1989 |
| 4630088 |
MOS dynamic ram |
Dec. 16, 1986 |
| 4459609 |
Charge-stabilized memory |
Jul. 10, 1984 |
| 4278989 |
Semiconductor device having cross wires |
Jul. 14, 1981 |
| 4206471 |
Semiconductor storage element and a process for the production thereof |
Jun. 3, 1980 |
| 4092736 |
Three electrode dynamic semiconductor memory cell with coincident selection |
May. 30, 1978 |
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