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Class Information
Number: 257/909
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Macrocell arrays (e.g., gate arrays with variable size or configuration of cells)
Description: Subject matter comprising plural geometric arrangements of groups of active solid-state devices, each group being connectable into a logic circuit, in one integrated, monolithic semiconductor chip. in which different groups differ from each other in size, complexity, or number of components.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7436078 |
Line layout structure of semiconductor memory device |
Oct. 14, 2008 |
| 7394156 |
Semiconductor integrated circuit device and method of producing the same |
Jul. 1, 2008 |
| 7368767 |
Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential |
May. 6, 2008 |
| 7348640 |
Memory device |
Mar. 25, 2008 |
| 7244986 |
Two-bit cell semiconductor memory device |
Jul. 17, 2007 |
| 7038294 |
Planar spiral inductor structure with patterned microelectronic structure integral thereto |
May. 2, 2006 |
| 6995436 |
Nonvolatile semiconductor memory device |
Feb. 7, 2006 |
| 6936891 |
Semiconductor memory device and manufacturing method therefor |
Aug. 30, 2005 |
| 6885044 |
Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates |
Apr. 26, 2005 |
| 6844576 |
Master slice type semiconductor integrated circuit and method for designing the same |
Jan. 18, 2005 |
| 6828624 |
Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough |
Dec. 7, 2004 |
| 6791162 |
Unit cell architecture for electrical interconnects |
Sep. 14, 2004 |
| 6765245 |
Gate array core cell for VLSI ASIC devices |
Jul. 20, 2004 |
| 6690076 |
Stitched circuits larger than the maximum reticle size in sub-micron process |
Feb. 10, 2004 |
| 6657318 |
Semiconductor integrated circuit device and method for mounting circuit blocks in semiconductor integrated circuit device |
Dec. 2, 2003 |
| 6642598 |
Semiconductor device |
Nov. 4, 2003 |
| 6601199 |
Memory-embedded LSI |
Jul. 29, 2003 |
| 6545310 |
Non-volatile memory with a serial transistor structure with isolated well and method of operation |
Apr. 8, 2003 |
| 6515374 |
Contact connection of metal interconnects of an integrated semiconductor chip |
Feb. 4, 2003 |
| 6476425 |
Master-slice system semiconductor integrated circuit and design method thereof |
Nov. 5, 2002 |
| 6452269 |
Semiconductor integrated circuit having power supply pin |
Sep. 17, 2002 |
| 6445017 |
Full CMOS SRAM cell |
Sep. 3, 2002 |
| 6396096 |
Design layout for a dense memory cell structure |
May. 28, 2002 |
| 6329678 |
Semiconductor memory array |
Dec. 11, 2001 |
| 6291843 |
Semiconductor memory device |
Sep. 18, 2001 |
| 6256604 |
Memory integrated with logic on a semiconductor chip and method of designing the same |
Jul. 3, 2001 |
| 6177693 |
Semiconductor device |
Jan. 23, 2001 |
| 6043522 |
Field effect transistor array including doped two-cell isolation region for preventing latchup |
Mar. 28, 2000 |
| 6043540 |
Static RAM having cell transistors with longer gate electrodes than transistors in the periphery of the cell |
Mar. 28, 2000 |
| RE36440 |
Integrated circuit SRAM cell layouts |
Dec. 14, 1999 |
| 5930187 |
One-chip LSI including a general memory and a logic |
Jul. 27, 1999 |
| 5923059 |
Integrated circuit cell architecture and routing scheme |
Jul. 13, 1999 |
| 5892558 |
Wire electrode structure based on 2 or 3 terminal device employed in a liquid crystal display |
Apr. 6, 1999 |
| 5869900 |
Sea-of-cells array of transistors |
Feb. 9, 1999 |
| 5814846 |
Cell apparatus and method for use in building complex integrated circuit devices |
Sep. 29, 1998 |
| 5789791 |
Multi-finger MOS transistor with reduced gate resistance |
Aug. 4, 1998 |
| 5763911 |
Micro-cellular capacitor for use in implantable medical devices |
Jun. 9, 1998 |
| 5742078 |
Integrated circuit SRAM cell layouts |
Apr. 21, 1998 |
| 5698876 |
Memory standard cell macro for semiconductor device |
Dec. 16, 1997 |
| 5656850 |
Microelectronic integrated circuit including hexagonal semiconductor "and" g |
Aug. 12, 1997 |
| 5635737 |
Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area |
Jun. 3, 1997 |
| 5616939 |
Semiconductor device including rectangular functional blocks having at least one common length |
Apr. 1, 1997 |
| 5581109 |
Semiconductor device |
Dec. 3, 1996 |
| 5539246 |
Microelectronic integrated circuit including hexagonal semiconductor "gate " device |
Jul. 23, 1996 |
| 5532509 |
Semiconductor inverter layout having improved electromigration characteristics in the output node |
Jul. 2, 1996 |
| 5521420 |
Fabricating a semiconductor with an insulative coating |
May. 28, 1996 |
| 5500544 |
Dynamic random access memory cell and method for fabricating the same |
Mar. 19, 1996 |
| 5436485 |
Transistor arrangement for forming basic cell of master-slice type semiconductor integrated circuit device and master-slice type semiconductor integrated circuit device |
Jul. 25, 1995 |
| 5399517 |
Method of routing three layer metal gate arrays using a channel router |
Mar. 21, 1995 |
| 5319228 |
Semiconductor memory device with trench-type capacitor |
Jun. 7, 1994 |
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