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Class Information
Number: 257/908
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines
Description: Subject matter comprising dynamic random access memory elements having transistors and capacitors, where memory elements connected to adjacent bit lines have transistors and capacitors which are not staggered but which lie along a straight line which is located between the adjacent bit lines of the device.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7456459 |
Design of low inductance embedded capacitor layer connections |
Nov. 25, 2008 |
| 7449742 |
Memory device with active layer of dendrimeric material |
Nov. 11, 2008 |
| 7375376 |
Semiconductor display device and method of manufacturing the same |
May. 20, 2008 |
| 7288806 |
DRAM arrays |
Oct. 30, 2007 |
| 7247902 |
Semiconductor device and method of manufacturing the same |
Jul. 24, 2007 |
| 7230300 |
Semiconductor device with peripheral trench |
Jun. 12, 2007 |
| 7211840 |
Transistor |
May. 1, 2007 |
| 7211867 |
Thin film memory, array, and operation method and manufacture method therefor |
May. 1, 2007 |
| 7189586 |
Test key for monitoring gate conductor to deep trench misalignment |
Mar. 13, 2007 |
| 7135731 |
Vertical DRAM and fabrication method thereof |
Nov. 14, 2006 |
| 7126154 |
Test structure for a single-sided buried strap DRAM memory cell array |
Oct. 24, 2006 |
| 7034408 |
Memory device and method of manufacturing a memory device |
Apr. 25, 2006 |
| 6974987 |
Semiconductor device |
Dec. 13, 2005 |
| 6974990 |
Selective polysilicon stud growth |
Dec. 13, 2005 |
| 6967348 |
Signal sharing circuit with microelectric die isolation features |
Nov. 22, 2005 |
| 6947324 |
Logic process DRAM |
Sep. 20, 2005 |
| 6936881 |
Capacitor that includes high permittivity capacitor dielectric |
Aug. 30, 2005 |
| 6930324 |
Device architecture and process for improved vertical memory arrays |
Aug. 16, 2005 |
| 6906371 |
Wordline gate contact for an MBIT transistor array layout |
Jun. 14, 2005 |
| 6897481 |
Semiconductor devices and manufacturing methods thereof |
May. 24, 2005 |
| 6890841 |
Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby |
May. 10, 2005 |
| 6876014 |
Interconnection structure of a semiconductor device |
Apr. 5, 2005 |
| 6872627 |
Selective formation of metal gate for dual gate oxide application |
Mar. 29, 2005 |
| 6861691 |
Selective polysilicon stud growth |
Mar. 1, 2005 |
| 6858497 |
Non-volatile semiconductor memory device and a method of producing the same |
Feb. 22, 2005 |
| 6853052 |
Semiconductor device having a buffer layer against stress |
Feb. 8, 2005 |
| 6849893 |
Semiconductor circuit structure and method for fabricating the semiconductor circuit structure |
Feb. 1, 2005 |
| 6849889 |
Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) |
Feb. 1, 2005 |
| 6803669 |
Integrated circuits having self-aligned metal contact structures |
Oct. 12, 2004 |
| 6794705 |
Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials |
Sep. 21, 2004 |
| 6791135 |
Semiconductor device with improved capacitive element and method of forming the same |
Sep. 14, 2004 |
| 6784474 |
Semiconductor memory device and method for fabricating the same |
Aug. 31, 2004 |
| 6747305 |
Memory address decode array with vertical transistors |
Jun. 8, 2004 |
| 6744089 |
Self-aligned lateral-transistor DRAM cell structure |
Jun. 1, 2004 |
| 6740918 |
Semiconductor memory device |
May. 25, 2004 |
| 6707088 |
Method of forming integrated circuitry, method of forming a capacitor, method of forming DRAM integrated circuitry and DRAM integrated category |
Mar. 16, 2004 |
| 6707092 |
Semiconductor memory having longitudinal cell structure |
Mar. 16, 2004 |
| 6703658 |
Non-volatile semiconductor memory device and its manufacturing method |
Mar. 9, 2004 |
| 6680502 |
Buried digit spacer separated capacitor array |
Jan. 20, 2004 |
| 6653739 |
Semiconductor device |
Nov. 25, 2003 |
| 6649962 |
Selective polysilicon stud growth |
Nov. 18, 2003 |
| 6621110 |
Semiconductor intergrated circuit device and a method of manufacture thereof |
Sep. 16, 2003 |
| 6586763 |
Organic light-emitting diodes and methods for assembly and emission control |
Jul. 1, 2003 |
| 6586805 |
Non-volatile semiconductor memory device |
Jul. 1, 2003 |
| 6573574 |
Cell array region of a NOR-type mask ROM device and fabricating method therefor |
Jun. 3, 2003 |
| 6567288 |
Methods for bi-level digit line architecture for high density DRAMS |
May. 20, 2003 |
| 6551846 |
Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration |
Apr. 22, 2003 |
| 6515374 |
Contact connection of metal interconnects of an integrated semiconductor chip |
Feb. 4, 2003 |
| 6476489 |
Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure |
Nov. 5, 2002 |
| 6472701 |
Non-volatile semiconductor memory device and its manufacturing method |
Oct. 29, 2002 |
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