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Class Information
Number: 257/907
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Folded bit line dram configuration
Description: Subject matter comprising an array of dynamic random access memory elements including differential sense amplifiers each connected to two different rows of memory cells, wherein the two rows of memory cells connected to a specific sense amplifier lie adjacent and parallel to each other on the same side of the sense amplifier.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8692379 Integrated circuit connector access region Apr. 8, 2014
8471320 Memory layout structure Jun. 25, 2013
8115246 Semiconductor device including protrusion type isolation layer Feb. 14, 2012
8093645 Non-volatile semiconductor memory device Jan. 10, 2012
8053831 Semiconductor integrated circuit devices having contacts formed of single-crystal materials Nov. 8, 2011
8030697 Cell structure of semiconductor device having an active region with a concave portion Oct. 4, 2011
7615815 Cell region layout of semiconductor device and method of forming contact pad using the same Nov. 10, 2009
7575992 Method of forming micro patterns in semiconductor devices Aug. 18, 2009
7545019 Integrated circuit including logic portion and memory portion Jun. 9, 2009
7541616 Semiconductor device Jun. 2, 2009
7517762 Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area Apr. 14, 2009
7449742 Memory device with active layer of dendrimeric material Nov. 11, 2008
7423300 Single-mask phase change memory element Sep. 9, 2008
7276725 Bit line barrier metal layer for semiconductor device and process for preparing the same Oct. 2, 2007
7268384 Semiconductor substrate having first and second pairs of word lines Sep. 11, 2007
7247902 Semiconductor device and method of manufacturing the same Jul. 24, 2007
7242602 Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs Jul. 10, 2007
7230343 High density memory array having increased channel widths Jun. 12, 2007
7005692 Memory cell arrays Feb. 28, 2006
6967887 Semiconductor memory device including a double-gate dynamic random access memory cell having reduced current leakage Nov. 22, 2005
6911687 Buried bit line-field isolation defined active semiconductor areas Jun. 28, 2005
6906370 Semiconductor component having a material reinforced contact area Jun. 14, 2005
6876014 Interconnection structure of a semiconductor device Apr. 5, 2005
6861691 Selective polysilicon stud growth Mar. 1, 2005
6849889 Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) Feb. 1, 2005
6839265 Bi-level digit line architecture for high density DRAMS Jan. 4, 2005
6777735 Semiconductor memory device having a metal plug or a landing pad Aug. 17, 2004
6696762 Bi-level digit line architecture for high density DRAMS Feb. 24, 2004
6649962 Selective polysilicon stud growth Nov. 18, 2003
6621110 Semiconductor intergrated circuit device and a method of manufacture thereof Sep. 16, 2003
6567288 Methods for bi-level digit line architecture for high density DRAMS May. 20, 2003
6551846 Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration Apr. 22, 2003
6512276 Semiconductor memory having an improved cell layout Jan. 28, 2003
6476489 Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure Nov. 5, 2002
6472708 Trench MOSFET with structure having low gate charge Oct. 29, 2002
6456518 Bi-level digit line architecture for high density drams Sep. 24, 2002
6438016 Semiconductor memory having dual port cell supporting hidden refresh Aug. 20, 2002
6429529 Bi-level digit line architecture for high density drams Aug. 6, 2002
6425046 Method for using a latched sense amplifier in a memory module as a high-speed cache memory Jul. 23, 2002
6424043 SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED I Jul. 23, 2002
6380575 DRAM trench cell Apr. 30, 2002
6380576 Selective polysilicon stud growth Apr. 30, 2002
6337815 Semiconductor memory device having redundant circuit Jan. 8, 2002
6333530 Semiconductor memory device having redundancy function Dec. 25, 2001
6326657 Semiconductor device having both memory and logic circuit and its manufacture Dec. 4, 2001
6310399 Semiconductor memory configuration with a bit-line twist Oct. 30, 2001
6303955 Dynamic random access memory with slanted active regions Oct. 16, 2001
6303966 SRAM cell having overlapping access transistor and drive transistor gates Oct. 16, 2001
6282113 Four F-squared gapless dual layer bitline DRAM array architecture Aug. 28, 2001
6259162 Method for reducing capactive coupling between conductive lines Jul. 10, 2001

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