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Class Information
Number: 257/900
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Mosfet type gate sidewall insulating spacer
Description: Subject matter wherein a metal oxide semiconductor field effect transistor with a gate electrode includes a relatively thick layer of electrically insulating material along the side wall of the gate electrode and wherein the source or drain region of the transistor has a distinct portion which is distant from the gate electrode and is aligned with the edge of the insulating material, so that the source or drain region is spaced from the gate electrode by the thickness of the insulating material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622732 |
Heterostructure nanotube devices |
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| 7582934 |
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| 7511340 |
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| 7501325 |
Method for fabricating semiconductor device |
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| 7482660 |
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Jan. 27, 2009 |
| 7470961 |
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| 7459758 |
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| 7456508 |
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| 7446354 |
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| 7439124 |
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| 7436029 |
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| 7435683 |
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Oct. 14, 2008 |
| RE40486 |
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Sep. 9, 2008 |
| 7405450 |
Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon |
Jul. 29, 2008 |
| 7378712 |
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May. 27, 2008 |
| 7375392 |
Gate structures having sidewall spacers formed using selective deposition |
May. 20, 2008 |
| 7375394 |
Fringing field induced localized charge trapping memory |
May. 20, 2008 |
| 7358571 |
Isolation spacer for thin SOI devices |
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| 7345296 |
Nanotube transistor and rectifying devices |
Mar. 18, 2008 |
| 7339230 |
Structure and method for making high density mosfet circuits with different height contact lines |
Mar. 4, 2008 |
| 7321155 |
Offset spacer formation for strained channel CMOS transistor |
Jan. 22, 2008 |
| 7301219 |
Electrically erasable programmable read only memory (EEPROM) cell and method for making the same |
Nov. 27, 2007 |
| 7291895 |
Integrated circuitry |
Nov. 6, 2007 |
| 7279758 |
N-channel MOSFETs comprising dual stressors, and methods for forming the same |
Oct. 9, 2007 |
| 7279746 |
High performance CMOS device structures and method of manufacture |
Oct. 9, 2007 |
| 7271414 |
Semiconductor device and method for fabricating the same |
Sep. 18, 2007 |
| 7265419 |
Semiconductor memory device with cell transistors having electrically floating channel bodies to store data |
Sep. 4, 2007 |
| 7256081 |
Structure and method to induce strain in a semiconductor device channel with stressed film under the gate |
Aug. 14, 2007 |
| 7253481 |
High performance MOS device with graded silicide |
Aug. 7, 2007 |
| 7253525 |
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Aug. 7, 2007 |
| 7242063 |
Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
Jul. 10, 2007 |
| 7227230 |
Low-K gate spacers by fluorine implantation |
Jun. 5, 2007 |
| 7211872 |
Device having recessed spacers for improved salicide resistance on polysilicon gates |
May. 1, 2007 |
| 7208803 |
Method of forming a raised source/drain and a semiconductor device employing the same |
Apr. 24, 2007 |
| 7205612 |
Fully silicided NMOS device for electrostatic discharge protection |
Apr. 17, 2007 |
| 7187031 |
Semiconductor device having a low dielectric constant film and manufacturing method thereof |
Mar. 6, 2007 |
| 7183662 |
Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties |
Feb. 27, 2007 |
| 7157374 |
Method for removing a cap from the gate of an embedded silicon germanium semiconductor device |
Jan. 2, 2007 |
| 7148552 |
High voltage transistor having side-wall width different from side-wall width of a low voltage transistor |
Dec. 12, 2006 |
| 7135707 |
Semiconductor device having insulated gate electrode |
Nov. 14, 2006 |
| 7132704 |
Transistor sidewall spacer stress modulation |
Nov. 7, 2006 |
| 7122833 |
Semiconductor integrated circuit and method of fabricating same |
Oct. 17, 2006 |
| 7119435 |
Semiconductor device with source/drain extension layer |
Oct. 10, 2006 |
| 7112847 |
Smooth fin topology in a FinFET device |
Sep. 26, 2006 |
| 7112859 |
Stepped tip junction with spacer layer |
Sep. 26, 2006 |
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