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Class Information
Number: 257/784
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Wire contact, lead, or bond
Description: Subject matter wherein the contact, lead or bond is a very flexible, elongated, small diameter filament made of electrically conductive material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6489673 |
Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers |
Dec. 3, 2002 |
| 6489674 |
Method for creating a die shrink insensitive semiconductor package and component therefor |
Dec. 3, 2002 |
| 6489680 |
Semiconductor device |
Dec. 3, 2002 |
| 6486538 |
Chip carrier having ventilation channels |
Nov. 26, 2002 |
| 6483175 |
Wiring board and semiconductor device using the same |
Nov. 19, 2002 |
| 6483178 |
Semiconductor device package structure |
Nov. 19, 2002 |
| 6483182 |
Integrated-circuit case |
Nov. 19, 2002 |
| 6483184 |
Semiconductor apparatus substrate, semiconductor apparatus, and method of manufacturing thereof and electronic apparatus |
Nov. 19, 2002 |
| 6479759 |
Submount, electronic assembly and process for producing the same |
Nov. 12, 2002 |
| 6479760 |
Printed wiring board for semiconductor plastic package |
Nov. 12, 2002 |
| 6479893 |
Ball-less clip bonding |
Nov. 12, 2002 |
| 6476468 |
Transverse hybrid LOC package |
Nov. 5, 2002 |
| 6476472 |
Integrated circuit package with improved ESD protection for no-connect pins |
Nov. 5, 2002 |
| 6476474 |
Dual-die package structure and method for fabricating the same |
Nov. 5, 2002 |
| 6476481 |
High current capacity semiconductor device package and lead frame with large area connection posts and modified outline |
Nov. 5, 2002 |
| 6476482 |
Chip-size integrated circuit package having slits formed in an insulator tape |
Nov. 5, 2002 |
| 6476505 |
Semiconductor device having pads, the intervals of which are adjusted and arranged in semiconductor chip corners |
Nov. 5, 2002 |
| 6476506 |
Packaged semiconductor with multiple rows of bond pads and method therefor |
Nov. 5, 2002 |
| 6472747 |
Mixed analog and digital integrated circuits |
Oct. 29, 2002 |
| 6472749 |
Semiconductor device having a shortened wiring length to reduce the size of a chip |
Oct. 29, 2002 |
| 6472764 |
Method and apparatus for implementing selected functionality on an integrated circuit device |
Oct. 29, 2002 |
| 6469380 |
Resin sealed semiconductor device utilizing a clad material heat sink |
Oct. 22, 2002 |
| 6469396 |
Integrated circuit chip having input/output terminals for testing and operation |
Oct. 22, 2002 |
| 6465878 |
Compliant microelectronic assemblies |
Oct. 15, 2002 |
| 6465885 |
Positioning of soldering pads in semiconductor diode package |
Oct. 15, 2002 |
| 6465886 |
Semiconductor device having circuit pattern and lands thereon |
Oct. 15, 2002 |
| 6465891 |
Integrated-circuit package with a quick-to-count finger layout design on substrate |
Oct. 15, 2002 |
| 6465896 |
Coils integrated in IC-package |
Oct. 15, 2002 |
| 6461897 |
Multichip module having a stacked chip arrangement |
Oct. 8, 2002 |
| 6462406 |
Semiconductor device and lead frame |
Oct. 8, 2002 |
| 6462424 |
Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure |
Oct. 8, 2002 |
| 6459154 |
Bonding pad structure of a semiconductor device and method of fabricating the same |
Oct. 1, 2002 |
| 6459163 |
Semiconductor device and method for fabricating the same |
Oct. 1, 2002 |
| 6455923 |
Apparatus and methods for providing substrate structures having metallic layers for microelectronics devices |
Sep. 24, 2002 |
| 6452262 |
Layout of Vdd and Vss balls in a four layer PBGA |
Sep. 17, 2002 |
| 6452279 |
Semiconductor device |
Sep. 17, 2002 |
| 6452283 |
Semiconductor chip with surface cover |
Sep. 17, 2002 |
| 6448634 |
Tape carrier, semiconductor assembly, semiconductor device and electronic instrument |
Sep. 10, 2002 |
| 6448636 |
Multi-layered integrated semiconductor device incorporating electrically connected integrated circuit chips and monitoring pads |
Sep. 10, 2002 |
| 6448639 |
Substrate having specific pad distribution |
Sep. 10, 2002 |
| 6448640 |
Ball array layout in chip assembly |
Sep. 10, 2002 |
| 6448641 |
Low-capacitance bonding pad for semiconductor device |
Sep. 10, 2002 |
| 6448659 |
Stacked die design with supporting O-ring |
Sep. 10, 2002 |
| 6444295 |
Method for improving integrated circuits bonding firmness |
Sep. 3, 2002 |
| 6445063 |
Method of forming a stack of packaged memory die and resulting apparatus |
Sep. 3, 2002 |
| 6445068 |
Semiconductor module |
Sep. 3, 2002 |
| 6445077 |
Semiconductor chip package |
Sep. 3, 2002 |
| 6445594 |
Semiconductor device having stacked semiconductor elements |
Sep. 3, 2002 |
| 6441481 |
Hermetically sealed microstructure package |
Aug. 27, 2002 |
| 6441488 |
Fan-out translator for a semiconductor package |
Aug. 27, 2002 |
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