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Class Information
Number: 257/776
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Cross-over arrangement, component or structure
Description: Subject matter wherein means are provided for electrically insulating electrical contact elements or leads which cross each other to do so without a short circuit therebetween.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6427324 |
Inherently robust repair process for thin film circuitry using UV laser |
Aug. 6, 2002 |
| 6424035 |
Semiconductor bilateral switch |
Jul. 23, 2002 |
| 6407460 |
Multilayer circuit board |
Jun. 18, 2002 |
| 6407455 |
Local interconnect using spacer-masked contact etch |
Jun. 18, 2002 |
| 6407434 |
Hexagonal architecture |
Jun. 18, 2002 |
| 6404056 |
Semiconductor integrated circuit |
Jun. 11, 2002 |
| 6400596 |
Semiconductor memory device using open data line arrangement |
Jun. 4, 2002 |
| 6400031 |
Semiconductor device having damascene interconnection structure that prevents void formation between interconnections |
Jun. 4, 2002 |
| 6396146 |
Semiconductor device and its manufacturing method |
May. 28, 2002 |
| 6392303 |
Digit line architecture for dynamic memory |
May. 21, 2002 |
| 6380635 |
Apparatus and methods for coupling conductive leads of semiconductor assemblies |
Apr. 30, 2002 |
| 6362524 |
Edge seal ring for copper damascene process and method for fabrication thereof |
Mar. 26, 2002 |
| 6355977 |
Semiconductor chip or device having a connecting member formed on a surface protective film |
Mar. 12, 2002 |
| 6351040 |
Method and apparatus for implementing selected functionality on an integrated circuit device |
Feb. 26, 2002 |
| 6331736 |
Utilization of die repattern layers for die internal connections |
Dec. 18, 2001 |
| 6329720 |
Tungsten local interconnect for silicon integrated circuit structures, and method of making same |
Dec. 11, 2001 |
| 6326693 |
Semiconductor integrated circuit device |
Dec. 4, 2001 |
| 6326695 |
Twisted bit line structures and method for making same |
Dec. 4, 2001 |
| 6313526 |
Semiconductor apparatus, Including thin film belt-like insulating tape |
Nov. 6, 2001 |
| 6310402 |
Semiconductor die having input/output cells and contact pads in the periphery of a substrate |
Oct. 30, 2001 |
| 6310399 |
Semiconductor memory configuration with a bit-line twist |
Oct. 30, 2001 |
| 6307263 |
Integrated semiconductor chip with modular dummy structures |
Oct. 23, 2001 |
| 6282113 |
Four F-squared gapless dual layer bitline DRAM array architecture |
Aug. 28, 2001 |
| 6281586 |
Integrated semiconductor circuit configuration having stabilized conductor tracks |
Aug. 28, 2001 |
| 6278186 |
Parasitic current barriers |
Aug. 21, 2001 |
| 6274936 |
Method for forming a contact during the formation of a semiconductor device |
Aug. 14, 2001 |
| 6261883 |
Semiconductor integrated circuit device, and fabrication process and designing method thereof |
Jul. 17, 2001 |
| 6262487 |
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method |
Jul. 17, 2001 |
| 6259162 |
Method for reducing capactive coupling between conductive lines |
Jul. 10, 2001 |
| 6255712 |
Semi-sacrificial diamond for air dielectric formation |
Jul. 3, 2001 |
| 6246121 |
High performance flip-chip semiconductor device |
Jun. 12, 2001 |
| 6246118 |
Low dielectric semiconductor device with rigid, conductively lined interconnection system |
Jun. 12, 2001 |
| 6245653 |
Method of filling an opening in an insulating layer |
Jun. 12, 2001 |
| 6243311 |
Digit line architecture for dynamic memory |
Jun. 5, 2001 |
| 6225646 |
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base |
May. 1, 2001 |
| 6222274 |
Bonding wire loop shape for a semiconductor device |
Apr. 24, 2001 |
| 6222275 |
Digit line architecture for dynamic memory |
Apr. 24, 2001 |
| 6211572 |
Semiconductor chip package with fan-in leads |
Apr. 3, 2001 |
| 6207986 |
Semiconductor integrated circuit device |
Mar. 27, 2001 |
| 6205044 |
Decoder connection configuration for memory chips with long bit lines |
Mar. 20, 2001 |
| 6194786 |
Integrated circuit package providing bond wire clearance over intervening conductive regions |
Feb. 27, 2001 |
| 6194777 |
Leadframes with selective palladium plating |
Feb. 27, 2001 |
| 6191486 |
Technique for producing interconnecting conductive links |
Feb. 20, 2001 |
| 6181014 |
Integrated circuit memory devices having highly integrated SOI memory cells therein |
Jan. 30, 2001 |
| 6177732 |
Multi-layer organic land grid array to minimize via inductance |
Jan. 23, 2001 |
| 6169331 |
Apparatus for electrically coupling bond pads of a microelectronic device |
Jan. 2, 2001 |
| 6160297 |
Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel |
Dec. 12, 2000 |
| 6160316 |
Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
Dec. 12, 2000 |
| 6160715 |
Translator for recessed flip-chip package |
Dec. 12, 2000 |
| 6150721 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines |
Nov. 21, 2000 |
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