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Class Information
Number: 257/776
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Cross-over arrangement, component or structure
Description: Subject matter wherein means are provided for electrically insulating electrical contact elements or leads which cross each other to do so without a short circuit therebetween.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6794724 |
Module for optical communications for converting light and differential signals |
Sep. 21, 2004 |
| 6787811 |
Wire connection structure and method of manufacturing the same |
Sep. 7, 2004 |
| 6787901 |
Stacked dies utilizing cross connection bonding wire |
Sep. 7, 2004 |
| 6784019 |
Intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same |
Aug. 31, 2004 |
| 6784542 |
Semiconductor device having a ball grid array and a fabrication process thereof |
Aug. 31, 2004 |
| 6784552 |
Structure having reduced lateral spacer erosion |
Aug. 31, 2004 |
| 6784551 |
Electronic device having a trimming possibility and at least one semiconductor chip and method for producing the electronic device |
Aug. 31, 2004 |
| 6781246 |
Semiconductor array device with single interconnection layer |
Aug. 24, 2004 |
| 6777809 |
BEOL decoupling capacitor |
Aug. 17, 2004 |
| 6777815 |
Configuration of conductive bumps and redistribution layer on a flip chip |
Aug. 17, 2004 |
| 6778403 |
Wiring board having terminal |
Aug. 17, 2004 |
| 6770972 |
Method for electrical interconnection employing salicide bridge |
Aug. 3, 2004 |
| 6768142 |
Circuit component placement |
Jul. 27, 2004 |
| 6767781 |
Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask |
Jul. 27, 2004 |
| 6765298 |
Substrate pads with reduced impedance mismatch and methods to fabricate substrate pads |
Jul. 20, 2004 |
| 6765296 |
Via-sea layout integrated circuits |
Jul. 20, 2004 |
| 6759747 |
Semiconductor device having damascene interconnection structure that prevents void formation between interconnections |
Jul. 6, 2004 |
| 6756679 |
Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device |
Jun. 29, 2004 |
| 6756688 |
Wiring board and its production method, semiconductor device and its production method, and electronic apparatus |
Jun. 29, 2004 |
| 6740979 |
Semiconductor device and LSI defect analyzing method using the same |
May. 25, 2004 |
| 6737745 |
Method for relieving bond stress in an under-bond-pad resistor |
May. 18, 2004 |
| 6737749 |
Resistive vias for controlling impedance and terminating I/O signals at the package level |
May. 18, 2004 |
| 6734572 |
Pad structure for bonding pad and probe pad and manufacturing method thereof |
May. 11, 2004 |
| 6731000 |
Folded-flex bondwire-less multichip power package |
May. 4, 2004 |
| 6720581 |
Mounting plate for a laser chip in a semiconductor laser device |
Apr. 13, 2004 |
| 6717260 |
Clip-type lead frame for source mounted die |
Apr. 6, 2004 |
| 6711810 |
Method of assembling a land grid array module |
Mar. 30, 2004 |
| 6700205 |
Semiconductor devices having contact plugs and local interconnects |
Mar. 2, 2004 |
| 6700204 |
Substrate for accommodating passive component |
Mar. 2, 2004 |
| 6696762 |
Bi-level digit line architecture for high density DRAMS |
Feb. 24, 2004 |
| 6686668 |
Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask |
Feb. 3, 2004 |
| 6680544 |
Flip-chip bump arrangement for decreasing impedance |
Jan. 20, 2004 |
| 6680536 |
Probe unit having resilient metal leads |
Jan. 20, 2004 |
| 6680543 |
Semiconductor integrated circuit and system |
Jan. 20, 2004 |
| 6674176 |
Wire bond package with core ring formed over I/O cells |
Jan. 6, 2004 |
| 6674177 |
Apparatus for implementing selected functionality on an integrated circuit device |
Jan. 6, 2004 |
| 6671198 |
Semiconductor device |
Dec. 30, 2003 |
| 6670710 |
Semiconductor device having multi-layered wiring |
Dec. 30, 2003 |
| 6664641 |
Wiring structure for an integrated circuit |
Dec. 16, 2003 |
| 6664642 |
Semiconductor integrated circuit device |
Dec. 16, 2003 |
| 6661041 |
Digitline architecture for dynamic memory |
Dec. 9, 2003 |
| 6657870 |
Die power distribution system |
Dec. 2, 2003 |
| 6657307 |
Semiconductor integrated circuit having functional macro with improved power line connection structure |
Dec. 2, 2003 |
| 6650015 |
Cavity-down ball grid array package with semiconductor chip solder ball |
Nov. 18, 2003 |
| 6639322 |
Flip-chip transition interface structure |
Oct. 28, 2003 |
| 6635960 |
Angled edge connections for multichip structures |
Oct. 21, 2003 |
| 6633057 |
Non-volatile semiconductor memory and fabricating method therefor |
Oct. 14, 2003 |
| 6633085 |
Method of selectively alloying interconnect regions by ion implantation |
Oct. 14, 2003 |
| 6624500 |
Thin-film electronic component and motherboard |
Sep. 23, 2003 |
| 6621171 |
Semiconductor device having a wire laid between pads |
Sep. 16, 2003 |
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