| |
 |
|
Class Information
Number: 257/776
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Cross-over arrangement, component or structure
Description: Subject matter wherein means are provided for electrically insulating electrical contact elements or leads which cross each other to do so without a short circuit therebetween.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5886410 |
Interconnect structure with hard mask and low dielectric constant materials |
Mar. 23, 1999 |
| 5883416 |
Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage |
Mar. 16, 1999 |
| 5880528 |
Energy absorbing structures to prevent damage to an integrated circuit |
Mar. 9, 1999 |
| 5874778 |
Embedded power and ground plane structure |
Feb. 23, 1999 |
| 5869867 |
FET semiconductor integrated circuit device having a planar element structure |
Feb. 9, 1999 |
| 5866924 |
Method and apparatus for routing a clock tree in an integrated circuit package |
Feb. 2, 1999 |
| 5864181 |
Bi-level digit line architecture for high density DRAMs |
Jan. 26, 1999 |
| 5861676 |
Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit |
Jan. 19, 1999 |
| 5838072 |
Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes |
Nov. 17, 1998 |
| 5838546 |
Mounting structure for a semiconductor circuit |
Nov. 17, 1998 |
| 5828121 |
Multi-level conduction structure for VLSI circuits |
Oct. 27, 1998 |
| 5821624 |
Semiconductor device assembly techniques using preformed planar structures |
Oct. 13, 1998 |
| 5818110 |
Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same |
Oct. 6, 1998 |
| 5818111 |
Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials |
Oct. 6, 1998 |
| 5814884 |
Commonly housed diverse semiconductor die |
Sep. 29, 1998 |
| 5812031 |
Ring oscillator having logic gates interconnected by spiral signal lines |
Sep. 22, 1998 |
| 5811882 |
On-chip shielding coaxial conductors for mixed-signal IC |
Sep. 22, 1998 |
| 5804854 |
Memory cell array |
Sep. 8, 1998 |
| 5804871 |
Lead on chip semiconductor device having bus bars and crossing leads |
Sep. 8, 1998 |
| 5801394 |
Structure for wiring reliability evaluation test and semiconductor device having the same |
Sep. 1, 1998 |
| 5793114 |
Self-aligned method for forming contact with zero offset to gate |
Aug. 11, 1998 |
| 5793099 |
Semiconductor device |
Aug. 11, 1998 |
| 5789797 |
Semiconductor device that suppresses electromagnetic noise |
Aug. 4, 1998 |
| 5783864 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect |
Jul. 21, 1998 |
| 5767546 |
Laternal power mosfet having metal strap layer to reduce distributed resistance |
Jun. 16, 1998 |
| 5764497 |
Circuit board connection method and connection structure |
Jun. 9, 1998 |
| 5761028 |
Transistor connection assembly having IGBT (X) cross ties |
Jun. 2, 1998 |
| 5757079 |
Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure |
May. 26, 1998 |
| 5753970 |
System having semiconductor die mounted in die-receiving area having different shape than die |
May. 19, 1998 |
| 5751057 |
Lead on chip lead frame design without jumpover wiring |
May. 12, 1998 |
| 5747867 |
Integrated circuit structure with interconnect formed along walls of silicon island |
May. 5, 1998 |
| 5748550 |
Multiple power line arrangement for a semiconductor memory device |
May. 5, 1998 |
| 5736774 |
High voltage integrated circuit, and high voltage level shift unit used for the same |
Apr. 7, 1998 |
| 5734187 |
Memory cell design with vertically stacked crossovers |
Mar. 31, 1998 |
| 5731620 |
Semiconductor device with reduced parasitic substrate capacitance |
Mar. 24, 1998 |
| 5726499 |
Semiconductor device having a minute contact hole |
Mar. 10, 1998 |
| 5723910 |
Semiconductor device having a MOS structure |
Mar. 3, 1998 |
| 5723908 |
Multilayer wiring structure |
Mar. 3, 1998 |
| 5723906 |
High-density wirebond chip interconnect for multi-chip modules |
Mar. 3, 1998 |
| 5719449 |
Flip-chip integrated circuit with improved testability |
Feb. 17, 1998 |
| 5717231 |
Antenna having elements with improved thermal impedance |
Feb. 10, 1998 |
| 5717229 |
Method and apparatus for routing a clock tree in an integrated circuit package |
Feb. 10, 1998 |
| 5691572 |
Interconnect structures for integrated circuits |
Nov. 25, 1997 |
| 5686743 |
Method of forming airbridged metallization for integrated circuit fabrication |
Nov. 11, 1997 |
| 5686699 |
Semiconductor board providing high signal pin utilization |
Nov. 11, 1997 |
| 5677574 |
Airbridge wiring structure for MMIC |
Oct. 14, 1997 |
| 5677554 |
FET having a dielectrically isolated gate connect |
Oct. 14, 1997 |
| 5675183 |
Hybrid multichip module and methods of fabricating same |
Oct. 7, 1997 |
| 5671173 |
Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines |
Sep. 23, 1997 |
| 5670815 |
Layout for noise reduction on a reference voltage |
Sep. 23, 1997 |
|
|
|
