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Class Information
Number: 257/775
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Varying width or thickness of conductor
Description: Subject matter wherein an electrical contact or lead has a width or thickness which varies over the length of the contact or lead.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6476481 |
High current capacity semiconductor device package and lead frame with large area connection posts and modified outline |
Nov. 5, 2002 |
| 6472763 |
Semiconductor device with bumps for pads |
Oct. 29, 2002 |
| 6469392 |
Conductive lines with reduced pitch |
Oct. 22, 2002 |
| 6465896 |
Coils integrated in IC-package |
Oct. 15, 2002 |
| 6465888 |
Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene |
Oct. 15, 2002 |
| 6462353 |
Method for fabricating a small area of contact between electrodes |
Oct. 8, 2002 |
| 6459156 |
Semiconductor device, a process for a semiconductor device, and a process for making a masking database |
Oct. 1, 2002 |
| 6455942 |
Method and apparatus for strapping a plurality of polysilicon lines in a semiconductor integrated circuit device |
Sep. 24, 2002 |
| 6455921 |
Fabricating plug and near-zero overlap interconnect line |
Sep. 24, 2002 |
| 6449838 |
Method of mounting a semiconductor device to a substrate |
Sep. 17, 2002 |
| 6448591 |
Metallization line layout |
Sep. 10, 2002 |
| 6448651 |
Semiconductor device having a multi-level metallization and its fabricating method |
Sep. 10, 2002 |
| 6448650 |
Fine pitch system and method for reinforcing bond pads in semiconductor devices |
Sep. 10, 2002 |
| 6448641 |
Low-capacitance bonding pad for semiconductor device |
Sep. 10, 2002 |
| 6441418 |
Spacer narrowed, dual width contact for charge gain reduction |
Aug. 27, 2002 |
| 6429528 |
Multichip semiconductor package |
Aug. 6, 2002 |
| 6429516 |
Structure for mounting a bare chip using an interposer |
Aug. 6, 2002 |
| 6424044 |
Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization |
Jul. 23, 2002 |
| 6420784 |
Electrochemical cobalt silicide liner for metal contact fills and damascene processes |
Jul. 16, 2002 |
| 6417572 |
Process for producing metal interconnections and product produced thereby |
Jul. 9, 2002 |
| 6407455 |
Local interconnect using spacer-masked contact etch |
Jun. 18, 2002 |
| 6404056 |
Semiconductor integrated circuit |
Jun. 11, 2002 |
| 6394821 |
Anisotropic conductive film and production method thereof |
May. 28, 2002 |
| 6392302 |
Polycide structure and method for forming polycide structure |
May. 21, 2002 |
| 6392307 |
Semiconductor device |
May. 21, 2002 |
| 6388322 |
Article comprising a mechanically compliant bump |
May. 14, 2002 |
| 6388321 |
Anisotropic conductive film and resin filling gap between a flip-chip and circuit board |
May. 14, 2002 |
| 6384484 |
Semiconductor device |
May. 7, 2002 |
| 6376913 |
Integrated semiconductor chip having leads to one or more external terminals |
Apr. 23, 2002 |
| 6376919 |
Circuit edit interconnect structure through the backside of an integrated circuit die |
Apr. 23, 2002 |
| 6373134 |
Semiconductor device and fabrication method introducing horizontal side-steps into vertical steps |
Apr. 16, 2002 |
| 6373143 |
Integrated circuit having wirebond pads suitable for probing |
Apr. 16, 2002 |
| 6369407 |
Semiconductor device |
Apr. 9, 2002 |
| 6366466 |
Multi-layer printed circuit board with signal traces of varying width |
Apr. 2, 2002 |
| 6362524 |
Edge seal ring for copper damascene process and method for fabrication thereof |
Mar. 26, 2002 |
| 6359301 |
Semiconductor device and method of manufacturing the same |
Mar. 19, 2002 |
| 6353243 |
Process for manufacturing an integrated circuit comprising an array of memory cells |
Mar. 5, 2002 |
| 6348737 |
Metallic interlocking structure |
Feb. 19, 2002 |
| 6348659 |
Resilient electrical interconnects having non-uniform cross-section |
Feb. 19, 2002 |
| 6340631 |
Method for laying out wide metal lines with embedded contacts/vias |
Jan. 22, 2002 |
| 6335567 |
Semiconductor device having stress reducing laminate and method for manufacturing the same |
Jan. 1, 2002 |
| 6333560 |
Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
Dec. 25, 2001 |
| 6331734 |
Semiconductor device and method for manufacturing the same |
Dec. 18, 2001 |
| 6329719 |
Semiconductor device |
Dec. 11, 2001 |
| 6326677 |
Ball grid array resistor network |
Dec. 4, 2001 |
| 6323557 |
Method and structure for improved alignment tolerance in multiple, singulated plugs |
Nov. 27, 2001 |
| 6320247 |
Unit type clip lead terminal, clip lead terminal connecting method, lead terminal connecting board, and method of producing board with lead terminals |
Nov. 20, 2001 |
| 6316836 |
Semiconductor device interconnection structure |
Nov. 13, 2001 |
| 6313537 |
Semiconductor device having multi-layered pad and a manufacturing method thereof |
Nov. 6, 2001 |
| 6313534 |
Ohmic electrode, method and multi-layered structure for making same |
Nov. 6, 2001 |
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