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Class Information
Number: 257/775
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Varying width or thickness of conductor
Description: Subject matter wherein an electrical contact or lead has a width or thickness which varies over the length of the contact or lead.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6849946 |
Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect |
Feb. 1, 2005 |
| 6849949 |
Thin stacked package |
Feb. 1, 2005 |
| 6847116 |
Chip-type semiconductor light-emitting device |
Jan. 25, 2005 |
| 6844214 |
Microelectromechanical system based sensors, sensor arrays, sensing systems, sensing methods and methods of fabrication |
Jan. 18, 2005 |
| 6844627 |
Metal film semiconductor device and a method for forming the same |
Jan. 18, 2005 |
| 6841408 |
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials |
Jan. 11, 2005 |
| 6841469 |
Semiconductor device and method of manufacturing the same |
Jan. 11, 2005 |
| 6838769 |
Dual damascene bond pad structure for lowering stress and allowing circuitry under pads |
Jan. 4, 2005 |
| 6836019 |
Semiconductor device having multilayer interconnection structure and manufacturing method thereof |
Dec. 28, 2004 |
| 6833323 |
Method for forming patterned features at a semiconductor wafer periphery to prevent metal peeling |
Dec. 21, 2004 |
| 6833557 |
Integrated circuit and a method of manufacturing an integrated circuit |
Dec. 21, 2004 |
| 6831365 |
Method and pattern for reducing interconnect failures |
Dec. 14, 2004 |
| 6828678 |
Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer |
Dec. 7, 2004 |
| 6822334 |
Semiconductor device having a layered wiring structure with hard mask covering |
Nov. 23, 2004 |
| 6822278 |
Localized field-inducding line and method for making the same |
Nov. 23, 2004 |
| 6815823 |
Copper metal structure for the reduction of intra-metal capacitance |
Nov. 9, 2004 |
| 6815827 |
Electrical connection between two faces of a substrate and manufacturing process |
Nov. 9, 2004 |
| 6815807 |
Method of fabricating a redundant pinout configuration for signal enhancement in an IC package |
Nov. 9, 2004 |
| 6812576 |
Fanned out interconnect via structure for electronic package substrates |
Nov. 2, 2004 |
| 6812577 |
Semiconductor contact structure having wide lower portion embedded in conductive material |
Nov. 2, 2004 |
| 6812575 |
Semiconductor device |
Nov. 2, 2004 |
| 6812555 |
Memory card substrate with alternating contacts |
Nov. 2, 2004 |
| 6809420 |
Characterization of induced shift on an overlay target using post-etch artifact wafers |
Oct. 26, 2004 |
| 6806565 |
Lead-frame-based semiconductor package and fabrication method thereof |
Oct. 19, 2004 |
| 6803649 |
Electronic assembly |
Oct. 12, 2004 |
| 6800886 |
Semiconductor device and method for fabricating the same |
Oct. 5, 2004 |
| 6798069 |
Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors |
Sep. 28, 2004 |
| 6794697 |
Asymmetric patterned magnetic memory |
Sep. 21, 2004 |
| 6794750 |
Semiconductor device |
Sep. 21, 2004 |
| 6794759 |
Semiconductor device, liquid crystal display device and method of manufacturing the semiconductor device |
Sep. 21, 2004 |
| 6791191 |
Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
Sep. 14, 2004 |
| 6787908 |
Pad metallization over active circuitry |
Sep. 7, 2004 |
| 6787913 |
Ohmic contact plug having an improved crack free TiN barrier metal in a contact hole and method of forming the same |
Sep. 7, 2004 |
| 6787907 |
Semiconductor device with dual damascene wiring |
Sep. 7, 2004 |
| 6784526 |
Integrated circuit device module |
Aug. 31, 2004 |
| 6784545 |
Semiconductor device having pad electrode connected to wire |
Aug. 31, 2004 |
| 6784552 |
Structure having reduced lateral spacer erosion |
Aug. 31, 2004 |
| 6784557 |
Semiconductor device including a diffusion layer formed between electrode portions |
Aug. 31, 2004 |
| 6783862 |
Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures |
Aug. 31, 2004 |
| 6781238 |
Semiconductor device and method of fabricating the same |
Aug. 24, 2004 |
| 6777332 |
Method for forming wiring structure |
Aug. 17, 2004 |
| 6777812 |
Semiconductor devices having protected plug contacts and upper interconnections |
Aug. 17, 2004 |
| 6777813 |
Fill pattern generation for spin-on-glass and related self-planarization deposition |
Aug. 17, 2004 |
| 6774024 |
Semiconductor integrated circuit device having multilevel interconnection |
Aug. 10, 2004 |
| 6770979 |
Semiconductor package and substrate thereof |
Aug. 3, 2004 |
| 6770936 |
Thin film transistors, and liquid crystal display device and electronic apparatus using the same |
Aug. 3, 2004 |
| 6768186 |
Semiconductor device and laminated leadframe package |
Jul. 27, 2004 |
| 6768142 |
Circuit component placement |
Jul. 27, 2004 |
| 6768189 |
High power chip scale package |
Jul. 27, 2004 |
| 6765296 |
Via-sea layout integrated circuits |
Jul. 20, 2004 |
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