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Class Information
Number: 257/775
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Varying width or thickness of conductor
Description: Subject matter wherein an electrical contact or lead has a width or thickness which varies over the length of the contact or lead.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6313541 |
Bone-pad with pad edge strengthening structure |
Nov. 6, 2001 |
| 6313536 |
Semicoductor device having a multilayered interconnection structure |
Nov. 6, 2001 |
| 6307264 |
Semiconductor device, active matrix substrate and process for production thereof |
Oct. 23, 2001 |
| 6307253 |
Lead frame and semiconductor device made by using it |
Oct. 23, 2001 |
| 6303990 |
Conductor path contacting arrangement and method |
Oct. 16, 2001 |
| 6303983 |
Apparatus for manufacturing resin-encapsulated semiconductor devices |
Oct. 16, 2001 |
| 6288447 |
Semiconductor device including a plurality of interconnection layers |
Sep. 11, 2001 |
| 6285083 |
Semiconductor device and mounting structure of a semiconductor device |
Sep. 4, 2001 |
| 6281540 |
Semiconductor memory device having bitlines of common height |
Aug. 28, 2001 |
| 6278189 |
High density integrated circuits using tapered and self-aligned contacts |
Aug. 21, 2001 |
| 6271601 |
Wire bonding method and apparatus and semiconductor device |
Aug. 7, 2001 |
| 6271589 |
Thick-film conductor circuit and production method therefor |
Aug. 7, 2001 |
| 6268661 |
Semiconductor device and method of its fabrication |
Jul. 31, 2001 |
| 6249013 |
Microwave-millimeter wave circuit device and method for manufacturing the same |
Jun. 19, 2001 |
| 6249032 |
Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof |
Jun. 19, 2001 |
| 6248429 |
Metallized recess in a substrate |
Jun. 19, 2001 |
| 6242795 |
Metal line structure and method of manufacturing the same |
Jun. 5, 2001 |
| 6236106 |
Wiring structure with divided wiring conductors to achieve planarity in an overlying SOG layer |
May. 22, 2001 |
| 6229214 |
Method for fabricating contact electrode of the semiconductor device |
May. 8, 2001 |
| 6222274 |
Bonding wire loop shape for a semiconductor device |
Apr. 24, 2001 |
| 6222268 |
Semiconductor device and method for manufacturing the same |
Apr. 24, 2001 |
| 6222738 |
Packaging structure for a semiconductor element flip-chip mounted on a mounting board having staggered bump connection location on the pads and method thereof |
Apr. 24, 2001 |
| 6215191 |
Compliant lead structures for microelectronic devices |
Apr. 10, 2001 |
| 6215195 |
Wire bonding with capillary realignment |
Apr. 10, 2001 |
| 6212077 |
Built-in inspection template for a printed circuit |
Apr. 3, 2001 |
| 6204550 |
Method and composition for reducing gate oxide damage during RF sputter clean |
Mar. 20, 2001 |
| 6204562 |
Wafer-level chip scale package |
Mar. 20, 2001 |
| 6188133 |
Semiconductor with plurality of connecting parts arranged on lower surface of a substrate |
Feb. 13, 2001 |
| 6188116 |
Structure of a polysilicon plug |
Feb. 13, 2001 |
| 6188135 |
Copper interconnect with top barrier layer |
Feb. 13, 2001 |
| 6188136 |
Semiconductor device including a wiring layer having a non-doped or high resistivity polycrystal silicon portion |
Feb. 13, 2001 |
| 6184586 |
Semiconductor device including a ball grid array |
Feb. 6, 2001 |
| 6181011 |
Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same |
Jan. 30, 2001 |
| 6177715 |
Integrated circuit having a level of metallization of variable thickness |
Jan. 23, 2001 |
| 6166442 |
Semiconductor device |
Dec. 26, 2000 |
| 6160316 |
Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
Dec. 12, 2000 |
| 6160297 |
Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel |
Dec. 12, 2000 |
| 6153937 |
Semiconductor device and method of the same |
Nov. 28, 2000 |
| 6150192 |
Apparatus and method for snap-on thermo-compression bonding |
Nov. 21, 2000 |
| 6147395 |
Method for fabricating a small area of contact between electrodes |
Nov. 14, 2000 |
| 6144090 |
Ball grid array package having electrodes on peripheral side surfaces of a package board |
Nov. 7, 2000 |
| 6140706 |
Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers |
Oct. 31, 2000 |
| 6137182 |
Method of reducing via and contact dimensions beyond photolithography equipment limits |
Oct. 24, 2000 |
| 6130482 |
Semiconductor device and method for fabricating the same |
Oct. 10, 2000 |
| 6127732 |
Semiconductor device having high aspect ratio contacts |
Oct. 3, 2000 |
| 6127734 |
Semiconductor device comprising a contact hole of varying width thru multiple insulating layers |
Oct. 3, 2000 |
| 6124640 |
Scalable and reliable integrated circuit inter-level dielectric |
Sep. 26, 2000 |
| 6114766 |
Integrated circuit with metal features presenting a larger landing area for vias |
Sep. 5, 2000 |
| 6114723 |
Flash memory cell using poly to poly tunneling for erase |
Sep. 5, 2000 |
| RE36837 |
Structure of contact between wiring layers in semiconductor integrated circuit device |
Aug. 29, 2000 |
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