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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7411301 |
Semiconductor integrated circuit device |
Aug. 12, 2008 |
| 7411294 |
Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer |
Aug. 12, 2008 |
| 7411285 |
Low profile stacked semiconductor chip package |
Aug. 12, 2008 |
| 7408241 |
Semiconductor device with a recessed bond pad |
Aug. 5, 2008 |
| 7408215 |
Dynamic random access memory |
Aug. 5, 2008 |
| 7408181 |
Phase-change memory device and method of manufacturing the same |
Aug. 5, 2008 |
| 7405474 |
Low cost thermally enhanced semiconductor package |
Jul. 29, 2008 |
| 7405470 |
Adaptable electronic storage apparatus |
Jul. 29, 2008 |
| 7405419 |
Unidirectionally conductive materials for interconnection |
Jul. 29, 2008 |
| 7402883 |
Back end of the line structures with liner and noble metal layer |
Jul. 22, 2008 |
| 7402515 |
Method of forming through-silicon vias with stress buffer collars and resulting devices |
Jul. 22, 2008 |
| 7400046 |
Semiconductor device with guard rings that are formed in each of the plural wiring layers |
Jul. 15, 2008 |
| 7400039 |
Semiconductor device and semiconductor package |
Jul. 15, 2008 |
| 7400028 |
Semiconductor device |
Jul. 15, 2008 |
| 7400025 |
Integrated circuit inductor with integrated vias |
Jul. 15, 2008 |
| 7399661 |
Method for making an integrated circuit substrate having embedded back-side access conductors and vias |
Jul. 15, 2008 |
| 7397130 |
Semiconductor devices with contact holes self-aligned in two directions |
Jul. 8, 2008 |
| 7397129 |
Interposers with flexible solder pad elements |
Jul. 8, 2008 |
| 7397128 |
Semiconductor device and method of manufacturing the same |
Jul. 8, 2008 |
| 7397125 |
Semiconductor device with bonding pad support structure |
Jul. 8, 2008 |
| 7394164 |
Semiconductor device having bumps in a same row for staggered probing |
Jul. 1, 2008 |
| 7394160 |
Printed wires arrangement for in-line memory (IMM) module |
Jul. 1, 2008 |
| 7394159 |
Delamination reduction between vias and conductive pads |
Jul. 1, 2008 |
| 7393782 |
Process for producing layer structures for signal distribution |
Jul. 1, 2008 |
| 7393770 |
Backside method for fabricating semiconductor components with conductive interconnects |
Jul. 1, 2008 |
| 7391115 |
Semiconductor device and manufacturing method thereof |
Jun. 24, 2008 |
| 7391114 |
Electrode pad section for external connection |
Jun. 24, 2008 |
| 7388439 |
Low pass filter and electronic device |
Jun. 17, 2008 |
| 7388293 |
Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions |
Jun. 17, 2008 |
| 7388256 |
Semiconductor device and a method of manufacturing the same |
Jun. 17, 2008 |
| 7385287 |
Preventing damage to low-k materials during resist stripping |
Jun. 10, 2008 |
| 7385283 |
Three dimensional integrated circuit and method of making the same |
Jun. 10, 2008 |
| 7382060 |
Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts |
Jun. 3, 2008 |
| 7382055 |
Integrated thin-film resistor with direct contact |
Jun. 3, 2008 |
| 7382054 |
Method for forming self-aligned contacts and local interconnects simultaneously |
Jun. 3, 2008 |
| 7382053 |
Power supply wiring structure |
Jun. 3, 2008 |
| 7382052 |
Post passivation interconnection schemes on top of IC chip |
Jun. 3, 2008 |
| 7382037 |
Semiconductor device with a peeling prevention layer |
Jun. 3, 2008 |
| 7382005 |
Circuit component with bump formed over chip |
Jun. 3, 2008 |
| 7378745 |
Package substrate for a semiconductor device having thermoplastic resin layers and conductive patterns |
May. 27, 2008 |
| 7378744 |
Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance |
May. 27, 2008 |
| 7378737 |
Structures and methods to enhance copper metallization |
May. 27, 2008 |
| 7375432 |
Via attached to a bond pad utilizing a tapered interconnect |
May. 20, 2008 |
| 7375428 |
Flip-chip bonding structure using multi chip module-deposited substrate |
May. 20, 2008 |
| 7372166 |
Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof |
May. 13, 2008 |
| 7372165 |
Method for making a semiconductor device having increased conductive material reliability |
May. 13, 2008 |
| 7372164 |
Semiconductor device with parallel interconnects |
May. 13, 2008 |
| 7372163 |
Semiconductor device and production method therefor |
May. 13, 2008 |
| 7372161 |
Post passivation interconnection schemes on top of the IC chips |
May. 13, 2008 |
| 7372143 |
Printed circuit board including via contributing to superior characteristic impedance |
May. 13, 2008 |
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