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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7528491 |
Semiconductor components and assemblies including vias of varying lateral dimensions |
May. 5, 2009 |
| 7528490 |
Semiconductor device and ferroelectric memory, and method for manufacturing semiconductor device |
May. 5, 2009 |
| 7528474 |
Stacked semiconductor package assembly having hollowed substrate |
May. 5, 2009 |
| 7528467 |
IC substrate with over voltage protection function |
May. 5, 2009 |
| 7525197 |
Barrier process/structure for transistor trench contact applications |
Apr. 28, 2009 |
| 7525196 |
Protection of seedlayer for electroplating |
Apr. 28, 2009 |
| 7525186 |
Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same |
Apr. 28, 2009 |
| 7521808 |
Wiring paterns formed by selective metal plating |
Apr. 21, 2009 |
| 7521807 |
Semiconductor device with inclined through holes |
Apr. 21, 2009 |
| 7521806 |
Chip spanning connection |
Apr. 21, 2009 |
| 7521805 |
Post passivation interconnection schemes on top of the IC chips |
Apr. 21, 2009 |
| 7521804 |
Semiconductor device preventing electrical short and method of manufacturing the same |
Apr. 21, 2009 |
| 7521798 |
Stacked imager package |
Apr. 21, 2009 |
| 7521793 |
Integrated circuit mounting for thermal stress relief useable in a multi-chip module |
Apr. 21, 2009 |
| 7521788 |
Semiconductor module with conductive element between chip packages |
Apr. 21, 2009 |
| 7521781 |
Integrated circuit package system with mold clamp line critical area having widened conductive traces |
Apr. 21, 2009 |
| 7521276 |
Compliant terminal mountings with vented spaces and methods |
Apr. 21, 2009 |
| 7518248 |
Inductive filters and methods of fabrication therefor |
Apr. 14, 2009 |
| 7518242 |
Semiconductor testing device |
Apr. 14, 2009 |
| 7518239 |
Semiconductor device with substrate having penetrating hole having a protrusion |
Apr. 14, 2009 |
| 7518169 |
MOS-transistor on SOI substrate with source via |
Apr. 14, 2009 |
| 7517792 |
Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof |
Apr. 14, 2009 |
| 7514797 |
Multi-die wafer level packaging |
Apr. 7, 2009 |
| 7514796 |
Semiconductor chip capable of being laminated and a semiconductor device including the lamination of a plurality of semiconductor chips |
Apr. 7, 2009 |
| 7514792 |
Semiconductor device and manufacturing method thereof |
Apr. 7, 2009 |
| 7514781 |
Circuit substrate and manufacturing method thereof |
Apr. 7, 2009 |
| 7514768 |
Package structure for a semiconductor device incorporating enhanced solder bump structure |
Apr. 7, 2009 |
| 7514671 |
Optical disk apparatus |
Apr. 7, 2009 |
| 7514355 |
Multilayer interconnection structure and method for forming the same |
Apr. 7, 2009 |
| 7514298 |
Printed wiring board for mounting semiconductor |
Apr. 7, 2009 |
| 7511379 |
Surface mountable direct chip attach device and method including integral integrated circuit |
Mar. 31, 2009 |
| 7511378 |
Enhancement of performance of a conductive wire in a multilayered substrate |
Mar. 31, 2009 |
| 7511365 |
Thermal enhanced low profile package structure |
Mar. 31, 2009 |
| 7511349 |
Contact or via hole structure with enlarged bottom critical dimension |
Mar. 31, 2009 |
| 7508079 |
Circuit substrate and method of manufacturing the same |
Mar. 24, 2009 |
| 7508078 |
Electronic device, method for manufacturing electronic device, contact hole of electronic device, method for forming contact hole of electronic device |
Mar. 24, 2009 |
| 7508059 |
Stacked chip package with redistribution lines |
Mar. 24, 2009 |
| 7507658 |
Semiconductor apparatus and method of fabricating the apparatus |
Mar. 24, 2009 |
| 7504731 |
Interconnect structure to reduce stress induced voiding effect |
Mar. 17, 2009 |
| 7504730 |
Memory elements |
Mar. 17, 2009 |
| 7504724 |
Semiconductor device |
Mar. 17, 2009 |
| 7504719 |
Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same |
Mar. 17, 2009 |
| 7504674 |
Electronic apparatus having a core conductive structure within an insulating layer |
Mar. 17, 2009 |
| 7501704 |
Integrated circuit chip with external pads and process for fabricating such a chip |
Mar. 10, 2009 |
| 7498676 |
Semiconductor device |
Mar. 3, 2009 |
| 7498660 |
Semiconductor device |
Mar. 3, 2009 |
| 7495340 |
Metal layer structure of semiconductor device |
Feb. 24, 2009 |
| 7495335 |
Method of reducing process steps in metal line protective structure formation |
Feb. 24, 2009 |
| 7495332 |
Multilayer printed wiring board |
Feb. 24, 2009 |
| 7495331 |
Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus |
Feb. 24, 2009 |
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