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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7425758 |
Metal core foldover package structures |
Sep. 16, 2008 |
| 7423340 |
Semiconductor package free of substrate and fabrication method thereof |
Sep. 9, 2008 |
| 7420285 |
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Sep. 2, 2008 |
| 7420284 |
Semiconductor device and manufacturing method thereof |
Sep. 2, 2008 |
| 7417327 |
IC chip package with cover |
Aug. 26, 2008 |
| 7417321 |
Via structure and process for forming the same |
Aug. 26, 2008 |
| 7417320 |
Substrate structure and manufacturing method of the same |
Aug. 26, 2008 |
| 7417319 |
Semiconductor device with connecting via and dummy via and method of manufacturing the same |
Aug. 26, 2008 |
| 7417318 |
Thick film circuit board, method of producing the same and integrated circuit device |
Aug. 26, 2008 |
| 7417317 |
Post passivation interconnection schemes on top of the IC chips |
Aug. 26, 2008 |
| 7417314 |
Semiconductor chip assembly with laterally aligned bumped terminal and filler |
Aug. 26, 2008 |
| 7417302 |
Semiconductor device and method of manufacturing the same |
Aug. 26, 2008 |
| 7416974 |
Method of manufacturing semiconductor device, and semiconductor device |
Aug. 26, 2008 |
| 7416973 |
Method of increasing the etch selectivity in a contact structure of semiconductor devices |
Aug. 26, 2008 |
| 7414316 |
Methods and apparatus for thermal isolation in vertically-integrated semiconductor devices |
Aug. 19, 2008 |
| 7414309 |
Encapsulated electronic part packaging structure |
Aug. 19, 2008 |
| 7414301 |
Printed circuit board with soldering lands |
Aug. 19, 2008 |
| 7414275 |
Multi-level interconnections for an integrated circuit chip |
Aug. 19, 2008 |
| 7414257 |
Switching device for configurable interconnect and method for preparing the same |
Aug. 19, 2008 |
| 7413978 |
Substrate, electro-optical device, electronic apparatus, method of forming substrate, method of forming electro-optical device, and method of forming electronic apparatus |
Aug. 19, 2008 |
| 7411305 |
Interconnect structure encased with high and low k interlevel dielectrics |
Aug. 12, 2008 |
| 7411303 |
Semiconductor assembly having substrate with electroplated contact pads |
Aug. 12, 2008 |
| 7411301 |
Semiconductor integrated circuit device |
Aug. 12, 2008 |
| 7411294 |
Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer |
Aug. 12, 2008 |
| 7411285 |
Low profile stacked semiconductor chip package |
Aug. 12, 2008 |
| 7408241 |
Semiconductor device with a recessed bond pad |
Aug. 5, 2008 |
| 7408215 |
Dynamic random access memory |
Aug. 5, 2008 |
| 7408181 |
Phase-change memory device and method of manufacturing the same |
Aug. 5, 2008 |
| 7405474 |
Low cost thermally enhanced semiconductor package |
Jul. 29, 2008 |
| 7405470 |
Adaptable electronic storage apparatus |
Jul. 29, 2008 |
| 7405419 |
Unidirectionally conductive materials for interconnection |
Jul. 29, 2008 |
| 7402883 |
Back end of the line structures with liner and noble metal layer |
Jul. 22, 2008 |
| 7402515 |
Method of forming through-silicon vias with stress buffer collars and resulting devices |
Jul. 22, 2008 |
| 7400046 |
Semiconductor device with guard rings that are formed in each of the plural wiring layers |
Jul. 15, 2008 |
| 7400039 |
Semiconductor device and semiconductor package |
Jul. 15, 2008 |
| 7400028 |
Semiconductor device |
Jul. 15, 2008 |
| 7400025 |
Integrated circuit inductor with integrated vias |
Jul. 15, 2008 |
| 7399661 |
Method for making an integrated circuit substrate having embedded back-side access conductors and vias |
Jul. 15, 2008 |
| 7397130 |
Semiconductor devices with contact holes self-aligned in two directions |
Jul. 8, 2008 |
| 7397129 |
Interposers with flexible solder pad elements |
Jul. 8, 2008 |
| 7397128 |
Semiconductor device and method of manufacturing the same |
Jul. 8, 2008 |
| 7397125 |
Semiconductor device with bonding pad support structure |
Jul. 8, 2008 |
| 7394164 |
Semiconductor device having bumps in a same row for staggered probing |
Jul. 1, 2008 |
| 7394160 |
Printed wires arrangement for in-line memory (IMM) module |
Jul. 1, 2008 |
| 7394159 |
Delamination reduction between vias and conductive pads |
Jul. 1, 2008 |
| 7393782 |
Process for producing layer structures for signal distribution |
Jul. 1, 2008 |
| 7393770 |
Backside method for fabricating semiconductor components with conductive interconnects |
Jul. 1, 2008 |
| 7391115 |
Semiconductor device and manufacturing method thereof |
Jun. 24, 2008 |
| 7391114 |
Electrode pad section for external connection |
Jun. 24, 2008 |
| 7388439 |
Low pass filter and electronic device |
Jun. 17, 2008 |
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