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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6849948 |
Contact structure and manufacturing method thereof |
Feb. 1, 2005 |
| 6847096 |
Semiconductor wafer having discharge structure to substrate |
Jan. 25, 2005 |
| 6844600 |
ESD/EOS protection structure for integrated circuit devices |
Jan. 18, 2005 |
| 6844617 |
Packaging mold with electrostatic discharge protection |
Jan. 18, 2005 |
| 6844620 |
Power layout structure of main bridge chip substrate and motherboard |
Jan. 18, 2005 |
| 6844627 |
Metal film semiconductor device and a method for forming the same |
Jan. 18, 2005 |
| 6841469 |
Semiconductor device and method of manufacturing the same |
Jan. 11, 2005 |
| 6841847 |
3-D spiral stacked inductor on semiconductor material |
Jan. 11, 2005 |
| 6841853 |
Semiconductor device having grooves to relieve stress between external electrodes and conductive patterns |
Jan. 11, 2005 |
| 6841875 |
Semiconductor device |
Jan. 11, 2005 |
| 6841883 |
Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
Jan. 11, 2005 |
| 6838767 |
Semiconductor device |
Jan. 4, 2005 |
| 6838769 |
Dual damascene bond pad structure for lowering stress and allowing circuitry under pads |
Jan. 4, 2005 |
| 6835960 |
Light emitting diode package structure |
Dec. 28, 2004 |
| 6836017 |
Protection of low-k ILD during damascene processing with thin liner |
Dec. 28, 2004 |
| 6836018 |
Wafer level package and method for manufacturing the same |
Dec. 28, 2004 |
| 6836019 |
Semiconductor device having multilayer interconnection structure and manufacturing method thereof |
Dec. 28, 2004 |
| 6836020 |
Electrical through wafer interconnects |
Dec. 28, 2004 |
| 6833613 |
Stacked semiconductor package having laser machined contacts |
Dec. 21, 2004 |
| 6833615 |
Via-in-pad with off-center geometry |
Dec. 21, 2004 |
| 6833623 |
Enhanced barrier liner formation for via |
Dec. 21, 2004 |
| 6833625 |
Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect |
Dec. 21, 2004 |
| 6831365 |
Method and pattern for reducing interconnect failures |
Dec. 14, 2004 |
| 6831366 |
Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer |
Dec. 14, 2004 |
| 6831367 |
Semiconductor device and method of manufacturing the same |
Dec. 14, 2004 |
| 6831368 |
Semiconductor device and method of manufacturing the same |
Dec. 14, 2004 |
| 6831369 |
Semiconductor structure having in-situ formed unit resistors and method for fabrication |
Dec. 14, 2004 |
| 6828233 |
Enhanced barrier liner formation for vias |
Dec. 7, 2004 |
| 6828680 |
Integrated circuit configuration using spacers as a diffusion barrier and method of producing such an integrated circuit configuration |
Dec. 7, 2004 |
| 6828686 |
Chip size stack package and method of fabricating the same |
Dec. 7, 2004 |
| 6825552 |
Connection components with anisotropic conductive material interconnection |
Nov. 30, 2004 |
| 6825553 |
Multichip wafer level packages and computing systems incorporating same |
Nov. 30, 2004 |
| 6825561 |
Structure and method for eliminating time dependent dielectric breakdown failure of low-k material |
Nov. 30, 2004 |
| 6825562 |
Damascene structure fabricated using a layer of silicon-based photoresist material |
Nov. 30, 2004 |
| 6825563 |
Slotted bonding pad |
Nov. 30, 2004 |
| 6825566 |
Semiconductor device with reduced interconnection capacity |
Nov. 30, 2004 |
| 6822316 |
Integrated circuit with improved interconnect structure and process for making same |
Nov. 23, 2004 |
| 6822320 |
Microelectronic connection components utilizing conductive cores and polymeric coatings |
Nov. 23, 2004 |
| 6822333 |
Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit |
Nov. 23, 2004 |
| 6822337 |
Window-type ball grid array semiconductor package |
Nov. 23, 2004 |
| 6818986 |
Semiconductor device and method of inspecting the same |
Nov. 16, 2004 |
| 6818997 |
Semiconductor constructions |
Nov. 16, 2004 |
| 6819565 |
Cavity-down ball grid array semiconductor package with heat spreader |
Nov. 16, 2004 |
| 6815714 |
Conductive structure in a semiconductor material |
Nov. 9, 2004 |
| 6815746 |
Semiconductor device and method of manufacturing the same |
Nov. 9, 2004 |
| 6815816 |
Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
Nov. 9, 2004 |
| 6815818 |
Electrode structure for use in an integrated circuit |
Nov. 9, 2004 |
| 6815820 |
Method for forming a semiconductor interconnect with multiple thickness |
Nov. 9, 2004 |
| 6815823 |
Copper metal structure for the reduction of intra-metal capacitance |
Nov. 9, 2004 |
| 6815825 |
Semiconductor devices having gradual slope contacts |
Nov. 9, 2004 |
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