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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6876078 |
Semiconductor interconnection structure with TaN and method of forming the same |
Apr. 5, 2005 |
| 6876079 |
Semiconductor device and method of manufacturing the same |
Apr. 5, 2005 |
| 6873046 |
Chip-scale package and carrier for use therewith |
Mar. 29, 2005 |
| 6873047 |
Semiconductor device and manufacturing method thereof |
Mar. 29, 2005 |
| 6873053 |
Semiconductor device with smoothed pad portion |
Mar. 29, 2005 |
| 6873054 |
Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus |
Mar. 29, 2005 |
| 6873057 |
Damascene interconnect with bi-layer capping film |
Mar. 29, 2005 |
| 6870230 |
Semiconductor device utilizing dummy features to form uniform sidewall structures |
Mar. 22, 2005 |
| 6870247 |
Interposer with a lateral recess in a slot to facilitate connection of intermediate conductive elements to bond pads of a semiconductor die with which the interposer is assembled |
Mar. 22, 2005 |
| 6870268 |
Integrated circuit devices formed through selective etching of an insulation layer to increase the self-aligned contact area adjacent a semiconductor region |
Mar. 22, 2005 |
| 6870274 |
Flash-preventing window ball grid array semiconductor package, method for fabricating the same, and chip carrier used in the semiconductor package |
Mar. 22, 2005 |
| 6867070 |
Bonding pad structure of a semiconductor device and method for manufacturing the same |
Mar. 15, 2005 |
| 6867121 |
Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction |
Mar. 15, 2005 |
| 6867491 |
Metal core integrated circuit package with electrically isolated regions and associated methods |
Mar. 15, 2005 |
| 6867497 |
Integrated circuitry |
Mar. 15, 2005 |
| 6867498 |
Metal line layout of an integrated circuit |
Mar. 15, 2005 |
| 6864171 |
Via density rules |
Mar. 8, 2005 |
| 6864545 |
Semiconductor device including low-resistance wires electrically connected to impurity layers |
Mar. 8, 2005 |
| 6864581 |
Etched metal trace with reduced RF impendance resulting from the skin effect |
Mar. 8, 2005 |
| 6864583 |
Wiring structure of semiconductor device |
Mar. 8, 2005 |
| 6861713 |
Integrated circuitry comprising insulative collars and integrated circuitry comprising sidewall spacers over a conductive line projecting outwardly from a first insulative material |
Mar. 1, 2005 |
| 6861737 |
Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same |
Mar. 1, 2005 |
| 6861740 |
Flip-chip die and flip-chip package substrate |
Mar. 1, 2005 |
| 6861746 |
Electrical circuit apparatus and methods for assembling same |
Mar. 1, 2005 |
| 6861750 |
Ball grid array package with multiple interposers |
Mar. 1, 2005 |
| 6861751 |
Etch stop layer for use in a self-aligned contact etch |
Mar. 1, 2005 |
| 6861758 |
Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process |
Mar. 1, 2005 |
| 6861759 |
Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same |
Mar. 1, 2005 |
| 6858936 |
Semiconductor device having an improved construction in the interlayer insulating film |
Feb. 22, 2005 |
| 6858937 |
Backend metallization method and device obtained therefrom |
Feb. 22, 2005 |
| 6858944 |
Bonding pad metal layer geometry design |
Feb. 22, 2005 |
| 6859916 |
Polygonal vias |
Feb. 22, 2005 |
| 6855967 |
Utilization of MACRO power routing area for buffer insertion |
Feb. 15, 2005 |
| 6856023 |
Semiconductor device and method of manufacturing semiconductor device |
Feb. 15, 2005 |
| 6856024 |
Semiconductor device with wiring embedded in trenches and vias |
Feb. 15, 2005 |
| 6856025 |
Chip and wafer integration process using vertical connections |
Feb. 15, 2005 |
| 6856026 |
Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
Feb. 15, 2005 |
| 6853023 |
Semiconductor memory cell configuration and a method for producing the configuration |
Feb. 8, 2005 |
| 6853043 |
Nitrogen-free antireflective coating for use with photolithographic patterning |
Feb. 8, 2005 |
| 6853059 |
Semiconductor package having improved adhesiveness and ground bonding |
Feb. 8, 2005 |
| 6853078 |
Semiconductor device and method for fabricating the same |
Feb. 8, 2005 |
| 6853081 |
Method for fabricating semiconductor integrated circuit |
Feb. 8, 2005 |
| 6853082 |
Method and structure for integrating metal insulator metal capacitor with copper |
Feb. 8, 2005 |
| 6853091 |
Printed circuit board and soldering structure for electronic parts thereto |
Feb. 8, 2005 |
| 6849946 |
Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect |
Feb. 1, 2005 |
| 6849948 |
Contact structure and manufacturing method thereof |
Feb. 1, 2005 |
| 6847096 |
Semiconductor wafer having discharge structure to substrate |
Jan. 25, 2005 |
| 6844600 |
ESD/EOS protection structure for integrated circuit devices |
Jan. 18, 2005 |
| 6844617 |
Packaging mold with electrostatic discharge protection |
Jan. 18, 2005 |
| 6844620 |
Power layout structure of main bridge chip substrate and motherboard |
Jan. 18, 2005 |
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