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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Physics
Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.


Patents under this class:
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Patent Number Title Of Patent Date Issued
6913950 Semiconductor device with chamfered substrate and method of making the same Jul. 5, 2005
6909128 Capacitance reduction by tunnel formation for use with a semiconductor device Jun. 21, 2005
6909174 Reference plane of integrated circuit packages Jun. 21, 2005
6909189 Semiconductor device with dummy structure Jun. 21, 2005
6909190 Dual-damascene dielectric structures Jun. 21, 2005
6909194 Electronic assembly having semiconductor component with polymer support member and method of fabrication Jun. 21, 2005
6909195 Trench etch process for low-k dielectrics Jun. 21, 2005
6909196 Method and structures for reduced parasitic capacitance in integrated circuit metallizations Jun. 21, 2005
6906419 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same Jun. 14, 2005
6903431 Substrate method and apparatus Jun. 7, 2005
6903442 Semiconductor component having backside pin contacts Jun. 7, 2005
6903443 Semiconductor component and interconnect having conductive members and contacts on opposing sides Jun. 7, 2005
6900532 Wafer level chip scale package May. 31, 2005
6900533 Apparatus for routing electrical signals May. 31, 2005
6900534 Direct attach chip scale package May. 31, 2005
6900546 Semiconductor memory device and method for manufacturing the same May. 31, 2005
6900548 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument May. 31, 2005
6897476 Test structure for determining electromigration and interlayer dielectric failure May. 24, 2005
6897479 ITO film contact structure, TFT substrate and manufacture thereof May. 24, 2005
6897555 Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die May. 24, 2005
6897557 Integrated electrical connector May. 24, 2005
6897561 Semiconductor power device having a diamond shaped metal interconnect scheme May. 24, 2005
6897563 Current crowding reduction technique using selective current injection May. 24, 2005
6897564 Plasma display panel having trench discharge cells with one or more electrodes formed therein and extended to outside of the trench May. 24, 2005
6894378 Electronic component with stacked semiconductor chips May. 17, 2005
6894392 Scaleable integrated data processing device May. 17, 2005
6894394 Semiconductor device, circuit board, electronic apparatus, and method for manufacturing semiconductor device May. 17, 2005
6891239 Integrated sensor and electronics package May. 10, 2005
6891258 Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit May. 10, 2005
6891260 Integrated circuit package substrate with high density routing mechanism May. 10, 2005
6891269 Embedded electroconductive layer structure May. 10, 2005
6891272 Multi-path via interconnection structures and methods for manufacturing the same May. 10, 2005
6887802 Method of manufacturing semiconductor device and semiconductor device May. 3, 2005
6888224 Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials May. 3, 2005
6888230 Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device May. 3, 2005
6888243 Semiconductor device May. 3, 2005
6888245 Semiconductor device May. 3, 2005
6888247 Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same May. 3, 2005
6888251 Metal spacer in single and dual damascene processing May. 3, 2005
6888252 Method of forming a conductive contact May. 3, 2005
6888253 Inexpensive wafer level MMIC chip packaging May. 3, 2005
6884650 Side-bonding method of flip-chip semiconductor device, MEMS device package and package method using the same Apr. 26, 2005
6884944 Multi-layer printed wiring boards having blind vias Apr. 26, 2005
6885098 Routing for multilayer ceramic substrates to reduce excessive via depth Apr. 26, 2005
6885102 Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts Apr. 26, 2005
6885105 Semiconductor device with copper wirings Apr. 26, 2005
6885109 Semiconductor device having a step-like section on the back side of the substrate, and method for manufacturing the same Apr. 26, 2005
6881974 Probe card for testing microelectronic components Apr. 19, 2005
6882038 Plating tail design for IC packages Apr. 19, 2005
6882041 Thermally enhanced metal capped BGA package Apr. 19, 2005

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