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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6954362 |
System and method for reducing apparent height of a board system |
Oct. 11, 2005 |
| 6951777 |
Methods for forming a slot with a laterally recessed area at an end thereof through an interposer or other carrier substrate |
Oct. 4, 2005 |
| 6952053 |
Metal bond pad for integrated circuits allowing improved probing ability of small pads |
Oct. 4, 2005 |
| 6952054 |
Semiconductor package having interconnect with conductive members |
Oct. 4, 2005 |
| 6949458 |
Self-aligned contact areas for sidewall image transfer formed conductors |
Sep. 27, 2005 |
| 6949828 |
Wiring structure having integral wiring portion and plug portion and method of forming the same |
Sep. 27, 2005 |
| 6949830 |
Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device |
Sep. 27, 2005 |
| 6949832 |
Semiconductor device including dissimilar element-diffused metal layer and manufacturing method thereof |
Sep. 27, 2005 |
| 6949835 |
Semiconductor device |
Sep. 27, 2005 |
| 6949839 |
Aligned buried structures formed by surface transformation of empty spaces in solid state materials |
Sep. 27, 2005 |
| 6946692 |
Interconnection utilizing diagonal routing |
Sep. 20, 2005 |
| 6946733 |
Ball grid array package having testing capability after mounting |
Sep. 20, 2005 |
| 6946735 |
Side-wall barrier structure and method of fabrication |
Sep. 20, 2005 |
| 6946737 |
Robust interlocking via |
Sep. 20, 2005 |
| 6946738 |
Semiconductor packaging substrate and method of producing the same |
Sep. 20, 2005 |
| 6946739 |
Layered semiconductor devices with conductive vias |
Sep. 20, 2005 |
| 6946325 |
Methods for packaging microelectronic devices |
Sep. 20, 2005 |
| 6943100 |
Method of fabricating a wiring board utilizing a conductive member having a reduced thickness |
Sep. 13, 2005 |
| 6943442 |
Electronic parts packaging structure having mutually connected electronic parts that are buried in a insulating film |
Sep. 13, 2005 |
| 6943446 |
Via construction for structural support |
Sep. 13, 2005 |
| 6943447 |
Thin film multi-layer wiring substrate having a coaxial wiring structure in at least one layer |
Sep. 13, 2005 |
| 6943451 |
Semiconductor devices containing a discontinuous cap layer and methods for forming same |
Sep. 13, 2005 |
| 6943452 |
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality |
Sep. 13, 2005 |
| 6940173 |
Interconnect structures incorporating low-k dielectric barrier films |
Sep. 6, 2005 |
| 6936918 |
MEMS device with conductive path through substrate |
Aug. 30, 2005 |
| 6936926 |
Wiring structure in a semiconductor device |
Aug. 30, 2005 |
| 6933599 |
Electromagnetic noise shielding in semiconductor packages using caged interconnect structures |
Aug. 23, 2005 |
| 6933601 |
Semiconductor connection substrate |
Aug. 23, 2005 |
| 6927469 |
Surface mountable light emitting or receiving device |
Aug. 9, 2005 |
| 6924552 |
Multilayered integrated circuit with extraneous conductive traces |
Aug. 2, 2005 |
| 6924555 |
Specially shaped contact via and integrated circuit therewith |
Aug. 2, 2005 |
| 6924868 |
Liquid crystal display device, method for fabricating the same, and portable telephone using the same |
Aug. 2, 2005 |
| 6921715 |
Semiconductor package and method of fabricating same |
Jul. 26, 2005 |
| 6921976 |
Semiconductor device including an island-like dielectric member embedded in a conductive pattern |
Jul. 26, 2005 |
| 6921977 |
Semiconductor package, method of production of same, and semiconductor device |
Jul. 26, 2005 |
| 6921978 |
Method to generate porous organic dielectric |
Jul. 26, 2005 |
| 6919508 |
Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing |
Jul. 19, 2005 |
| 6919635 |
High density microvia substrate with high wireability |
Jul. 19, 2005 |
| 6919637 |
Interconnect structure for an integrated circuit and method of fabrication |
Jul. 19, 2005 |
| 6919639 |
Multiple copper vias for integrated circuit metallization and methods of fabricating same |
Jul. 19, 2005 |
| 6916745 |
Structure and method for forming a trench MOSFET having self-aligned features |
Jul. 12, 2005 |
| 6917110 |
Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
Jul. 12, 2005 |
| 6917114 |
Semiconductor device and method of fabricating the same |
Jul. 12, 2005 |
| 6917115 |
Alignment pattern for a semiconductor device manufacturing process |
Jul. 12, 2005 |
| 6917116 |
Electrical connection device between two tracks of an integrated circuit |
Jul. 12, 2005 |
| 6913950 |
Semiconductor device with chamfered substrate and method of making the same |
Jul. 5, 2005 |
| 6909128 |
Capacitance reduction by tunnel formation for use with a semiconductor device |
Jun. 21, 2005 |
| 6909174 |
Reference plane of integrated circuit packages |
Jun. 21, 2005 |
| 6909189 |
Semiconductor device with dummy structure |
Jun. 21, 2005 |
| 6909190 |
Dual-damascene dielectric structures |
Jun. 21, 2005 |
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