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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7095061 |
Contacting scheme for large and small area semiconductor light emitting flip chip devices |
Aug. 22, 2006 |
| 7095073 |
High K artificial lattices for capacitor applications to use in Cu or Al BEOL |
Aug. 22, 2006 |
| 7095083 |
Methods for making semiconductor structures having high-speed areas and high-density areas |
Aug. 22, 2006 |
| 7095114 |
Semiconductor device with via hole group generating high frequency electromagnetic bonding, manufacturing method thereof, and monolithic microwave integrated circuit |
Aug. 22, 2006 |
| 7095118 |
High-Frequency semiconductor device with noise elimination characteristic |
Aug. 22, 2006 |
| 7095120 |
Semiconductor integrated circuit device with a connective portion for multilevel interconnection |
Aug. 22, 2006 |
| 7091613 |
Elongated bonding pad for wire bonding and sort probing |
Aug. 15, 2006 |
| 7091618 |
Semiconductor device and method of manufacturing the same |
Aug. 15, 2006 |
| 7088001 |
Semiconductor integrated circuit device with a metallization structure |
Aug. 8, 2006 |
| 7088002 |
Interconnect |
Aug. 8, 2006 |
| 7088003 |
Structures and methods for integration of ultralow-k dielectrics with improved reliability |
Aug. 8, 2006 |
| 7084508 |
Semiconductor device with multiple layer insulating film |
Aug. 1, 2006 |
| 7084509 |
Electronic package with filled blinds vias |
Aug. 1, 2006 |
| 7084510 |
Semiconductor device and method of manufacturing the same |
Aug. 1, 2006 |
| 7080446 |
Wiring board sheet and its manufacturing method, multilayer board and its manufacturing method |
Jul. 25, 2006 |
| 7081408 |
Method of creating a tapered via using a receding mask and resulting structure |
Jul. 25, 2006 |
| 7081650 |
Interposer with signal and power supply through vias |
Jul. 25, 2006 |
| 7081665 |
Semiconductor component having thinned substrate, backside pin contacts and circuit side contacts |
Jul. 25, 2006 |
| 7078788 |
Microelectronic substrates with integrated devices |
Jul. 18, 2006 |
| 7078810 |
Semiconductor device and fabrication method thereof |
Jul. 18, 2006 |
| 7078812 |
Routing differential signal lines in a substrate |
Jul. 18, 2006 |
| 7078813 |
Semiconductor device with double barrier film |
Jul. 18, 2006 |
| 7078814 |
Method of forming a semiconductor device having air gaps and the structure so formed |
Jul. 18, 2006 |
| 7078817 |
Multiple copper vias for integrated circuit metallization |
Jul. 18, 2006 |
| 7075179 |
System for implementing a configurable integrated circuit |
Jul. 11, 2006 |
| 7075182 |
Semiconductor device |
Jul. 11, 2006 |
| 7075185 |
Routing vias in a substrate from bypass capacitor pads |
Jul. 11, 2006 |
| 7076750 |
Method and apparatus for generating trenches for vias |
Jul. 11, 2006 |
| 7071097 |
Method for improved process latitude by elongated via integration |
Jul. 4, 2006 |
| 7071510 |
Capacitor of an integrated circuit device and method of manufacturing the same |
Jul. 4, 2006 |
| 7071517 |
Self-aligned semiconductor contact structures and methods for fabricating the same |
Jul. 4, 2006 |
| 7071557 |
Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same |
Jul. 4, 2006 |
| 7071563 |
Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
Jul. 4, 2006 |
| 7071564 |
Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration |
Jul. 4, 2006 |
| 7071569 |
Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection |
Jul. 4, 2006 |
| 7067417 |
Methods of removing resistive remnants from contact holes using silicidation |
Jun. 27, 2006 |
| 7067919 |
Semiconductor device |
Jun. 27, 2006 |
| 7067925 |
Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment |
Jun. 27, 2006 |
| 7067928 |
Method of forming a bonding pad structure |
Jun. 27, 2006 |
| 7064395 |
Semiconductor device and method for fabricating the same |
Jun. 20, 2006 |
| 7064441 |
Semiconductor device and method of manufacturing the same |
Jun. 20, 2006 |
| 7061041 |
Memory device |
Jun. 13, 2006 |
| 7061094 |
Multilayer printed circuit board including first and second signal traces and a first ground trace |
Jun. 13, 2006 |
| 7061115 |
Interconnect line selectively isolated from an underlying contact plug |
Jun. 13, 2006 |
| 7061118 |
Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
Jun. 13, 2006 |
| 7056820 |
Bond pad |
Jun. 6, 2006 |
| 7056823 |
Backend metallization method and device obtained therefrom |
Jun. 6, 2006 |
| 7056828 |
Sidewall spacer structure for self-aligned contact and method for forming the same |
Jun. 6, 2006 |
| 7057270 |
Systems and methods for stacking chip components |
Jun. 6, 2006 |
| 7057287 |
Dual damascene integration of ultra low dielectric constant porous materials |
Jun. 6, 2006 |
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