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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7193432 |
VPA logic circuits |
Mar. 20, 2007 |
| 7193327 |
Barrier structure for semiconductor devices |
Mar. 20, 2007 |
| 7193297 |
Semiconductor device, method for manufacturing the same, circuit substrate and electronic device |
Mar. 20, 2007 |
| 7190080 |
Semiconductor chip assembly with embedded metal pillar |
Mar. 13, 2007 |
| 7190079 |
Selective capping of copper wiring |
Mar. 13, 2007 |
| 7190078 |
Interlocking via for package via integrity |
Mar. 13, 2007 |
| 7190077 |
Semiconductor structure integrated under a pad |
Mar. 13, 2007 |
| 7190074 |
Reconstructed semiconductor wafers including alignment droplets contacting alignment vias |
Mar. 13, 2007 |
| 7187085 |
Semiconductor device including dual damascene interconnections |
Mar. 6, 2007 |
| 7187084 |
Damascene method employing composite etch stop layer |
Mar. 6, 2007 |
| 7187081 |
Polycarbosilane buried etch stops in interconnect structures |
Mar. 6, 2007 |
| 7187080 |
Semiconductor device with a conductive layer including a copper layer with a dopant |
Mar. 6, 2007 |
| 7183654 |
Providing a via with an increased via contact area |
Feb. 27, 2007 |
| 7183653 |
Via including multiple electrical paths |
Feb. 27, 2007 |
| 7180193 |
Via recess in underlying conductive line |
Feb. 20, 2007 |
| 7180192 |
Semiconductor device |
Feb. 20, 2007 |
| 7180191 |
Semiconductor device and method of manufacturing a semiconductor device |
Feb. 20, 2007 |
| 7180187 |
Interlayer connector for preventing delamination of semiconductor device |
Feb. 20, 2007 |
| 7180180 |
Stacked device underfill and a method of fabrication |
Feb. 20, 2007 |
| 7180170 |
Lead-free integrated circuit package structure |
Feb. 20, 2007 |
| 7180149 |
Semiconductor package with through-hole |
Feb. 20, 2007 |
| 7180011 |
Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design |
Feb. 20, 2007 |
| 7179733 |
Method of forming contact holes and electronic device formed thereby |
Feb. 20, 2007 |
| 7176578 |
Method for processing a thin film substrate |
Feb. 13, 2007 |
| 7176577 |
Semiconductor device |
Feb. 13, 2007 |
| 7176556 |
Semiconductor system-in-package |
Feb. 13, 2007 |
| 7176533 |
Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus |
Feb. 13, 2007 |
| 7173339 |
Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure |
Feb. 6, 2007 |
| 7170182 |
Semiconductor device with reduced interconnect capacitance |
Jan. 30, 2007 |
| 7170178 |
Capacitive integrated circuit structure |
Jan. 30, 2007 |
| 7170177 |
Semiconductor apparatus |
Jan. 30, 2007 |
| 7170174 |
Contact structure and contact liner process |
Jan. 30, 2007 |
| 7170152 |
Wafer level semiconductor package with build-up layer and method for fabricating the same |
Jan. 30, 2007 |
| 7166923 |
Semiconductor device, electro-optical unit, and electronic apparatus |
Jan. 23, 2007 |
| 7166906 |
Package with barrier wall and method for manufacturing the same |
Jan. 23, 2007 |
| 7164206 |
Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer |
Jan. 16, 2007 |
| 7164198 |
Multilayered substrate for semiconductor device |
Jan. 16, 2007 |
| 7161240 |
Insitu-cooled electrical assemblage |
Jan. 9, 2007 |
| 7161237 |
Flip chip packaging using recessed interposer terminals |
Jan. 9, 2007 |
| 7157797 |
Semiconductor device with suppressed copper migration |
Jan. 2, 2007 |
| 7154184 |
Interconnection structure of semiconductor device |
Dec. 26, 2006 |
| 7154183 |
Semiconductor device having multilevel interconnection |
Dec. 26, 2006 |
| 7154182 |
Localized slots for stress relieve in copper |
Dec. 26, 2006 |
| 7154181 |
Semiconductor device and method of manufacturing the same |
Dec. 26, 2006 |
| 7148575 |
Semiconductor device having bonding pad above low-k dielectric film |
Dec. 12, 2006 |
| 7148572 |
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation |
Dec. 12, 2006 |
| 7148554 |
Discrete electronic component arrangement including anchoring, thermally conductive pad |
Dec. 12, 2006 |
| 7148535 |
Zero capacitance bondpad utilizing active negative capacitance |
Dec. 12, 2006 |
| 7145241 |
Semiconductor device having a multilayer interconnection structure and fabrication process thereof |
Dec. 5, 2006 |
| 7145228 |
Microelectronic devices |
Dec. 5, 2006 |
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