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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7242098 |
Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment |
Jul. 10, 2007 |
| 7242094 |
Semiconductor device having capacitor formed in multilayer wiring structure |
Jul. 10, 2007 |
| 7239019 |
Selectively converted inter-layer dielectric |
Jul. 3, 2007 |
| 7239002 |
Integrated circuit device |
Jul. 3, 2007 |
| 7235884 |
Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via |
Jun. 26, 2007 |
| 7233073 |
Semiconductor device and method for fabricating the same |
Jun. 19, 2007 |
| 7233063 |
Borderless contact structures |
Jun. 19, 2007 |
| 7230340 |
Post passivation interconnection schemes on top of the IC chips |
Jun. 12, 2007 |
| 7230338 |
Semiconductor device that improves electrical connection reliability |
Jun. 12, 2007 |
| 7230337 |
Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same |
Jun. 12, 2007 |
| 7230335 |
Inspection methods and structures for visualizing and/or detecting specific chip structures |
Jun. 12, 2007 |
| 7230318 |
RF and MMIC stackable micro-modules |
Jun. 12, 2007 |
| 7229913 |
Stitched micro-via to enhance adhesion and mechanical strength |
Jun. 12, 2007 |
| 7227266 |
Interconnect structure to reduce stress induced voiding effect |
Jun. 5, 2007 |
| 7227264 |
Semiconductor device and method for manufacturing semiconductor device |
Jun. 5, 2007 |
| 7227256 |
Die-up ball grid array package with printed circuit board attachable heat spreader |
Jun. 5, 2007 |
| 7224069 |
Dummy structures extending from seal ring into active circuit area of integrated circuit chip |
May. 29, 2007 |
| 7224068 |
Stable metal structure with tungsten plug |
May. 29, 2007 |
| 7224064 |
Semiconductor device having conductive interconnections and porous and nonporous insulating portions |
May. 29, 2007 |
| 7224060 |
Integrated circuit with protective moat |
May. 29, 2007 |
| 7224046 |
Multilayer wiring board incorporating carbon fibers and glass fibers |
May. 29, 2007 |
| 7222776 |
Printed wiring board and manufacturing method therefor |
May. 29, 2007 |
| 7221059 |
Wafer level semiconductor component having thinned, encapsulated dice and polymer dam |
May. 22, 2007 |
| 7221050 |
Substrate having a functionally gradient coefficient of thermal expansion |
May. 22, 2007 |
| 7218530 |
Enhanced blind hole termination of pin to PCB |
May. 15, 2007 |
| 7217995 |
Apparatus for stacking electrical components using insulated and interconnecting via |
May. 15, 2007 |
| 7215033 |
Wafer level stack structure for system-in-package and method thereof |
May. 8, 2007 |
| 7215032 |
Triaxial through-chip connection |
May. 8, 2007 |
| 7215029 |
Multilayer interconnection structure of a semiconductor |
May. 8, 2007 |
| 7215025 |
Wafer scale semiconductor structure |
May. 8, 2007 |
| 7211899 |
Circuit substrate and method for fabricating the same |
May. 1, 2007 |
| 7211897 |
Semiconductor device and method for fabricating the same |
May. 1, 2007 |
| 7211896 |
Semiconductor device and method of manufacturing the same |
May. 1, 2007 |
| 7211850 |
Semiconductor device with specifically shaped contact holes |
May. 1, 2007 |
| 7211510 |
Stacking circuit elements |
May. 1, 2007 |
| 7208843 |
Routing design to minimize electromigration damage to solder bumps |
Apr. 24, 2007 |
| 7208839 |
Semiconductor component assemblies having interconnects |
Apr. 24, 2007 |
| 7208838 |
Semiconductor device, circuit board, and electronic instrument suitable for stacking and having a through hole |
Apr. 24, 2007 |
| 7208831 |
Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer |
Apr. 24, 2007 |
| 7208828 |
Semiconductor package with wire bonded stacked dice and multi-layer metal bumps |
Apr. 24, 2007 |
| 7208348 |
Methods of fabricating a via-in-pad with off-center geometry |
Apr. 24, 2007 |
| 7205668 |
Multi-layer printed circuit board wiring layout |
Apr. 17, 2007 |
| 7205649 |
Ball grid array copper balancing |
Apr. 17, 2007 |
| 7205613 |
Insulating substrate for IC packages having integral ESD protection |
Apr. 17, 2007 |
| 7205486 |
Thermally isolated via structure |
Apr. 17, 2007 |
| 7202567 |
Semiconductor device and manufacturing method for the same |
Apr. 10, 2007 |
| 7202566 |
Crossed power strapped layout for full CMOS circuit design |
Apr. 10, 2007 |
| 7202556 |
Semiconductor package having substrate with multi-layer metal bumps |
Apr. 10, 2007 |
| 7199473 |
Integrated low-k hard mask |
Apr. 3, 2007 |
| 7196423 |
Interconnect structure with dielectric barrier and fabrication method thereof |
Mar. 27, 2007 |
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