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Class Information
Number: 257/774
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration > Via (interconnection hole) shape
Description: Subject matter wherein the shape or configuration of an electrical contact or lead is determined by the shape of a hole through an insulating layer through which the contact extends.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7459793 |
Methods for forming contact hole, for manufacturing circuit board and for manufacturing electro-optical device |
Dec. 2, 2008 |
| 7459792 |
Via layout with via groups placed in interlocked arrangement |
Dec. 2, 2008 |
| 7459791 |
Post passivation interconnection schemes on top of IC chip |
Dec. 2, 2008 |
| 7459790 |
Post passivation interconnection schemes on top of the IC chips |
Dec. 2, 2008 |
| 7459786 |
Semiconductor device |
Dec. 2, 2008 |
| 7459777 |
Semiconductor package containing multi-layered semiconductor chips |
Dec. 2, 2008 |
| 7459763 |
Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material |
Dec. 2, 2008 |
| 7453152 |
Device having reduced chemical mechanical planarization |
Nov. 18, 2008 |
| 7453151 |
Methods for lateral current carrying capability improvement in semiconductor devices |
Nov. 18, 2008 |
| 7453150 |
Three-dimensional face-to-face integration assembly |
Nov. 18, 2008 |
| 7453141 |
Semiconductor device package, method of manufacturing the same, and semiconductor device |
Nov. 18, 2008 |
| 7452214 |
Interconnect assemblies, and methods of forming interconnects, between conductive contact bumps and conductive contact pads |
Nov. 18, 2008 |
| 7449784 |
Device package and methods for the fabrication and testing thereof |
Nov. 11, 2008 |
| 7449783 |
Nonlinear via arrays for resistors to reduce systematic circuit offsets |
Nov. 11, 2008 |
| 7446418 |
Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
Nov. 4, 2008 |
| 7446398 |
Bump pattern design for flip chip semiconductor package |
Nov. 4, 2008 |
| 7444614 |
Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal |
Oct. 28, 2008 |
| 7443035 |
Method of forming a penetration electrode and substrate having a penetration electrode |
Oct. 28, 2008 |
| 7443034 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 28, 2008 |
| 7443033 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 28, 2008 |
| 7443031 |
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation |
Oct. 28, 2008 |
| 7443030 |
Thin silicon based substrate |
Oct. 28, 2008 |
| 7443029 |
Adhesion of copper and etch stop layer for copper alloy |
Oct. 28, 2008 |
| 7443020 |
Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit |
Oct. 28, 2008 |
| 7442641 |
Integrated ball and via package and formation process |
Oct. 28, 2008 |
| 7439628 |
Method for improved process latitude by elongated via integration |
Oct. 21, 2008 |
| 7439627 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 21, 2008 |
| 7439626 |
Post passivation interconnection schemes on top of IC chip |
Oct. 21, 2008 |
| 7439623 |
Semiconductor device having via connecting between interconnects |
Oct. 21, 2008 |
| 7436069 |
Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode |
Oct. 14, 2008 |
| 7436068 |
Components for film forming device |
Oct. 14, 2008 |
| 7432598 |
Semiconductor device |
Oct. 7, 2008 |
| 7432597 |
Semiconductor device and method of manufacturing the same |
Oct. 7, 2008 |
| 7432192 |
Post ECP multi-step anneal/H.sub.2 treatment to reduce film impurity |
Oct. 7, 2008 |
| 7425758 |
Metal core foldover package structures |
Sep. 16, 2008 |
| 7423340 |
Semiconductor package free of substrate and fabrication method thereof |
Sep. 9, 2008 |
| 7420285 |
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Sep. 2, 2008 |
| 7420284 |
Semiconductor device and manufacturing method thereof |
Sep. 2, 2008 |
| 7417327 |
IC chip package with cover |
Aug. 26, 2008 |
| 7417321 |
Via structure and process for forming the same |
Aug. 26, 2008 |
| 7417320 |
Substrate structure and manufacturing method of the same |
Aug. 26, 2008 |
| 7417319 |
Semiconductor device with connecting via and dummy via and method of manufacturing the same |
Aug. 26, 2008 |
| 7417318 |
Thick film circuit board, method of producing the same and integrated circuit device |
Aug. 26, 2008 |
| 7417317 |
Post passivation interconnection schemes on top of the IC chips |
Aug. 26, 2008 |
| 7417314 |
Semiconductor chip assembly with laterally aligned bumped terminal and filler |
Aug. 26, 2008 |
| 7417302 |
Semiconductor device and method of manufacturing the same |
Aug. 26, 2008 |
| 7416974 |
Method of manufacturing semiconductor device, and semiconductor device |
Aug. 26, 2008 |
| 7416973 |
Method of increasing the etch selectivity in a contact structure of semiconductor devices |
Aug. 26, 2008 |
| 7414316 |
Methods and apparatus for thermal isolation in vertically-integrated semiconductor devices |
Aug. 19, 2008 |
| 7414309 |
Encapsulated electronic part packaging structure |
Aug. 19, 2008 |
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