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Class Information
Number: 257/773
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration
Description: Subject matter in which an electrical contact or lead has a specific configuration or shape.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6841408 |
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials |
Jan. 11, 2005 |
| 6841853 |
Semiconductor device having grooves to relieve stress between external electrodes and conductive patterns |
Jan. 11, 2005 |
| 6841864 |
Semiconductor integrated circuit device, mounting board, and device and board assembly |
Jan. 11, 2005 |
| 6841871 |
Semiconductor device utilizing pads of different sizes connected to an antenna |
Jan. 11, 2005 |
| 6841880 |
Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing |
Jan. 11, 2005 |
| 6838755 |
Leadframe for integrated circuit chips having low resistance connections |
Jan. 4, 2005 |
| 6838769 |
Dual damascene bond pad structure for lowering stress and allowing circuitry under pads |
Jan. 4, 2005 |
| 6838773 |
Semiconductor chip and semiconductor device using the semiconductor chip |
Jan. 4, 2005 |
| 6838774 |
Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
Jan. 4, 2005 |
| 6835579 |
Method of monitoring internal voltage and controlling a parameter of an integrated circuit |
Dec. 28, 2004 |
| 6836018 |
Wafer level package and method for manufacturing the same |
Dec. 28, 2004 |
| 6836019 |
Semiconductor device having multilayer interconnection structure and manufacturing method thereof |
Dec. 28, 2004 |
| 6833611 |
Semiconductor device |
Dec. 21, 2004 |
| 6833620 |
Apparatus having reduced input output area and method thereof |
Dec. 21, 2004 |
| 6833622 |
Semiconductor topography having an inactive region formed from a dummy structure pattern |
Dec. 21, 2004 |
| 6833323 |
Method for forming patterned features at a semiconductor wafer periphery to prevent metal peeling |
Dec. 21, 2004 |
| 6833557 |
Integrated circuit and a method of manufacturing an integrated circuit |
Dec. 21, 2004 |
| 6833607 |
Resin-molded semiconductor device that includes at least one additional electronic part |
Dec. 21, 2004 |
| 6831006 |
Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner |
Dec. 14, 2004 |
| 6831365 |
Method and pattern for reducing interconnect failures |
Dec. 14, 2004 |
| 6828614 |
Semiconductor constructions, and methods of forming semiconductor constructions |
Dec. 7, 2004 |
| 6828652 |
Fuse structure for semiconductor device |
Dec. 7, 2004 |
| 6828677 |
Precision electroplated solder bumps and method for manufacturing thereof |
Dec. 7, 2004 |
| 6828678 |
Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer |
Dec. 7, 2004 |
| 6828686 |
Chip size stack package and method of fabricating the same |
Dec. 7, 2004 |
| 6825553 |
Multichip wafer level packages and computing systems incorporating same |
Nov. 30, 2004 |
| 6825556 |
Integrated circuit package design with non-orthogonal die cut out |
Nov. 30, 2004 |
| 6825563 |
Slotted bonding pad |
Nov. 30, 2004 |
| 6825565 |
Semiconductor device |
Nov. 30, 2004 |
| 6822265 |
Light emitting diode |
Nov. 23, 2004 |
| 6822287 |
Array of integrated circuit units with strapping lines to prevent punch through |
Nov. 23, 2004 |
| 6822327 |
Flip-chip interconnected with increased current-carrying capability |
Nov. 23, 2004 |
| 6822331 |
Method of mounting a circuit component and joint structure therefor |
Nov. 23, 2004 |
| 6822332 |
Fine line circuitization |
Nov. 23, 2004 |
| 6822333 |
Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit |
Nov. 23, 2004 |
| 6822334 |
Semiconductor device having a layered wiring structure with hard mask covering |
Nov. 23, 2004 |
| 6818996 |
Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps |
Nov. 16, 2004 |
| 6818997 |
Semiconductor constructions |
Nov. 16, 2004 |
| 6819001 |
Interposer, interposer package and device assembly employing the same |
Nov. 16, 2004 |
| 6815714 |
Conductive structure in a semiconductor material |
Nov. 9, 2004 |
| 6815807 |
Method of fabricating a redundant pinout configuration for signal enhancement in an IC package |
Nov. 9, 2004 |
| 6815816 |
Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
Nov. 9, 2004 |
| 6815820 |
Method for forming a semiconductor interconnect with multiple thickness |
Nov. 9, 2004 |
| 6812486 |
Conductive structure and method of forming the structure |
Nov. 2, 2004 |
| 6812512 |
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture |
Nov. 2, 2004 |
| 6812549 |
Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument |
Nov. 2, 2004 |
| 6812571 |
Low capacitance wiring layout and method for making same |
Nov. 2, 2004 |
| 6812573 |
Semiconductor device and method for manufacturing the same |
Nov. 2, 2004 |
| 6812574 |
Semiconductor storage device and method of fabricating the same |
Nov. 2, 2004 |
| 6809420 |
Characterization of induced shift on an overlay target using post-etch artifact wafers |
Oct. 26, 2004 |
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