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Class Information
Number: 257/773
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration
Description: Subject matter in which an electrical contact or lead has a specific configuration or shape.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7115996 |
Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped |
Oct. 3, 2006 |
| 7115991 |
Method for creating barriers for copper diffusion |
Oct. 3, 2006 |
| 7115956 |
Conductive film as the connector for thin film display device |
Oct. 3, 2006 |
| 7109586 |
System for reducing or eliminating semiconductor device wire sweep |
Sep. 19, 2006 |
| 7109575 |
Low-cost flexible film package module and method of manufacturing the same |
Sep. 19, 2006 |
| 7105858 |
Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density |
Sep. 12, 2006 |
| 7105861 |
Electronic device contact structures |
Sep. 12, 2006 |
| 7105871 |
Semiconductor device |
Sep. 12, 2006 |
| 7105873 |
Semiconductor device and method for patterning |
Sep. 12, 2006 |
| 7105918 |
Interposer with flexible solder pad elements and methods of manufacturing the same |
Sep. 12, 2006 |
| 7105926 |
Routing scheme for differential pairs in flip chip substrates |
Sep. 12, 2006 |
| 7105927 |
Structure of dummy pattern in semiconductor device |
Sep. 12, 2006 |
| 7105933 |
Semiconductor integrated circuit device and manufacturing method of the same |
Sep. 12, 2006 |
| 7102217 |
Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same |
Sep. 5, 2006 |
| 7102237 |
ASIC customization with predefined via mask |
Sep. 5, 2006 |
| 7098524 |
Electroplated wire layout for package sawing |
Aug. 29, 2006 |
| 7098540 |
Electrical interconnect with minimal parasitic capacitance |
Aug. 29, 2006 |
| 7099175 |
Semiconductor memory integrated circuit |
Aug. 29, 2006 |
| 7095107 |
Ball assignment schemes for integrated circuit packages |
Aug. 22, 2006 |
| 7091565 |
Efficient transistor structure |
Aug. 15, 2006 |
| 7091570 |
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact |
Aug. 15, 2006 |
| 7091592 |
Stacked package for electronic elements and packaging method thereof |
Aug. 15, 2006 |
| 7091593 |
Circuit board with built-in electronic component and method for manufacturing the same |
Aug. 15, 2006 |
| 7091616 |
Semiconductor device having a leading wiring layer |
Aug. 15, 2006 |
| 7091617 |
Design and layout techniques for low parasitic capacitance in analog circuit applications |
Aug. 15, 2006 |
| 7091620 |
Semiconductor device and manufacturing method thereof |
Aug. 15, 2006 |
| 7088001 |
Semiconductor integrated circuit device with a metallization structure |
Aug. 8, 2006 |
| 7088008 |
Electronic package with optimized circuitization pattern |
Aug. 8, 2006 |
| 7084490 |
Leads under chip IC package |
Aug. 1, 2006 |
| 7084507 |
Integrated circuit device and method of producing the same |
Aug. 1, 2006 |
| 7081677 |
Thermoelectric module |
Jul. 25, 2006 |
| 7078822 |
Microelectronic device interconnects |
Jul. 18, 2006 |
| 7075179 |
System for implementing a configurable integrated circuit |
Jul. 11, 2006 |
| 7075184 |
Semiconductor device and manufacturing method, circuit board and electronic device thereof |
Jul. 11, 2006 |
| 7071557 |
Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same |
Jul. 4, 2006 |
| 7071560 |
Semiconductor device and a method of manufacturing the same and designing the same |
Jul. 4, 2006 |
| 7071563 |
Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
Jul. 4, 2006 |
| 7071569 |
Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection |
Jul. 4, 2006 |
| 7071574 |
Semiconductor device and its wiring method |
Jul. 4, 2006 |
| 7067919 |
Semiconductor device |
Jun. 27, 2006 |
| 7064431 |
Electronic assembly having select spacing of rows and columns of contacts to allow for routing of traces to the contacts |
Jun. 20, 2006 |
| 7064442 |
Integrated circuit package device |
Jun. 20, 2006 |
| 7064450 |
Semiconductor die with high density offset-inline bond arrangement |
Jun. 20, 2006 |
| 7060537 |
Microchip controller board manufacturing method |
Jun. 13, 2006 |
| 7061083 |
Semiconductor devices |
Jun. 13, 2006 |
| 7061094 |
Multilayer printed circuit board including first and second signal traces and a first ground trace |
Jun. 13, 2006 |
| 7061095 |
Printed circuit board conductor channeling |
Jun. 13, 2006 |
| 7061112 |
Semiconductor device including an electrical contact connected to an interconnection |
Jun. 13, 2006 |
| 7061115 |
Interconnect line selectively isolated from an underlying contact plug |
Jun. 13, 2006 |
| 7061116 |
Arrangement of vias in a substrate to support a ball grid array |
Jun. 13, 2006 |
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