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Class Information
Number: 257/773
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified configuration
Description: Subject matter in which an electrical contact or lead has a specific configuration or shape.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7459792 |
Via layout with via groups placed in interlocked arrangement |
Dec. 2, 2008 |
| 7459791 |
Post passivation interconnection schemes on top of IC chip |
Dec. 2, 2008 |
| 7459790 |
Post passivation interconnection schemes on top of the IC chips |
Dec. 2, 2008 |
| 7459789 |
Bonding method of flexible film and display bonded thereby |
Dec. 2, 2008 |
| 7459787 |
Multi-layered copper line structure of semiconductor device and method for forming the same |
Dec. 2, 2008 |
| 7459777 |
Semiconductor package containing multi-layered semiconductor chips |
Dec. 2, 2008 |
| 7456501 |
Semiconductor structure having recess with conductive metal |
Nov. 25, 2008 |
| 7454831 |
Method for mounting an electronic element on a wiring board |
Nov. 25, 2008 |
| 7453158 |
Pad over active circuit system and method with meshed support structure |
Nov. 18, 2008 |
| 7453150 |
Three-dimensional face-to-face integration assembly |
Nov. 18, 2008 |
| 7453112 |
Integrated circuit memory cells and methods of forming |
Nov. 18, 2008 |
| 7449778 |
Power semiconductor module as H-bridge circuit and method for producing the same |
Nov. 11, 2008 |
| 7446417 |
Semiconductor integrated circuit device and fabrication method thereof |
Nov. 4, 2008 |
| 7446405 |
Wafer level chip scale package (WLCSP) with high reliability against thermal stress |
Nov. 4, 2008 |
| 7446047 |
Metal structure with sidewall passivation and method |
Nov. 4, 2008 |
| 7446038 |
Interlayer interconnect of three-dimensional memory and method for manufacturing the same |
Nov. 4, 2008 |
| 7443038 |
Flip-chip image sensor packages |
Oct. 28, 2008 |
| 7443034 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 28, 2008 |
| 7443033 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 28, 2008 |
| 7443020 |
Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit |
Oct. 28, 2008 |
| 7442641 |
Integrated ball and via package and formation process |
Oct. 28, 2008 |
| 7439627 |
Post passivation interconnection schemes on top of the IC chips |
Oct. 21, 2008 |
| 7439626 |
Post passivation interconnection schemes on top of IC chip |
Oct. 21, 2008 |
| 7439625 |
Circuit board |
Oct. 21, 2008 |
| 7439623 |
Semiconductor device having via connecting between interconnects |
Oct. 21, 2008 |
| 7439615 |
Semiconductor component comprising an integrated semiconductor chip and a chip housing, and electronic device |
Oct. 21, 2008 |
| 7432594 |
Semiconductor chip, electrically connections therefor |
Oct. 7, 2008 |
| 7432564 |
Pixel structure |
Oct. 7, 2008 |
| 7429799 |
Land patterns for a semiconductor stacking structure and method therefor |
Sep. 30, 2008 |
| 7429797 |
Electronic device and carrier substrate |
Sep. 30, 2008 |
| 7429780 |
Fuse circuit and semiconductor device including the same |
Sep. 30, 2008 |
| 7427809 |
Repairable three-dimensional semiconductor subsystem |
Sep. 23, 2008 |
| 7427801 |
Integrated circuit transformer devices for on-chip millimeter-wave applications |
Sep. 23, 2008 |
| 7425758 |
Metal core foldover package structures |
Sep. 16, 2008 |
| 7425745 |
Semiconductor device and method for manufacturing the same |
Sep. 16, 2008 |
| 7423346 |
Post passivation interconnection process and structures |
Sep. 9, 2008 |
| 7423340 |
Semiconductor package free of substrate and fabrication method thereof |
Sep. 9, 2008 |
| 7420286 |
Reduced inductance in ball grid array packages |
Sep. 2, 2008 |
| 7420285 |
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Sep. 2, 2008 |
| 7420284 |
Semiconductor device and manufacturing method thereof |
Sep. 2, 2008 |
| 7420280 |
Reduced stress under bump metallization structure |
Sep. 2, 2008 |
| 7417327 |
IC chip package with cover |
Aug. 26, 2008 |
| 7417321 |
Via structure and process for forming the same |
Aug. 26, 2008 |
| 7417317 |
Post passivation interconnection schemes on top of the IC chips |
Aug. 26, 2008 |
| 7417309 |
Circuit device and portable device with symmetrical arrangement |
Aug. 26, 2008 |
| 7414314 |
Semiconductor device and manufacturing method thereof |
Aug. 19, 2008 |
| 7414301 |
Printed circuit board with soldering lands |
Aug. 19, 2008 |
| 7414291 |
Semiconductor device and method of manufacturing the same |
Aug. 19, 2008 |
| 7411304 |
Semiconductor interconnect having conductive spring contacts |
Aug. 12, 2008 |
| 7411303 |
Semiconductor assembly having substrate with electroplated contact pads |
Aug. 12, 2008 |
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