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Class Information
Number: 257/758
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)
Description: Subject matter wherein there are plural layers of metal forming electrical contact material, the layers being separated by intervening layers of insulator material.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7459787 |
Multi-layered copper line structure of semiconductor device and method for forming the same |
Dec. 2, 2008 |
| 7459786 |
Semiconductor device |
Dec. 2, 2008 |
| 7459761 |
High performance system-on-chip using post passivation process |
Dec. 2, 2008 |
| 7459389 |
Method of forming a semiconductor device having air gaps and the structure so formed |
Dec. 2, 2008 |
| 7456048 |
Semiconducting device with folded interposer |
Nov. 25, 2008 |
| 7453158 |
Pad over active circuit system and method with meshed support structure |
Nov. 18, 2008 |
| 7453152 |
Device having reduced chemical mechanical planarization |
Nov. 18, 2008 |
| 7452803 |
Method for fabricating chip structure |
Nov. 18, 2008 |
| 7452802 |
Method of forming metal wiring for high voltage element |
Nov. 18, 2008 |
| 7446418 |
Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
Nov. 4, 2008 |
| 7446417 |
Semiconductor integrated circuit device and fabrication method thereof |
Nov. 4, 2008 |
| 7446416 |
Barrier material formation in integrated circuit structures |
Nov. 4, 2008 |
| 7443031 |
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation |
Oct. 28, 2008 |
| 7443030 |
Thin silicon based substrate |
Oct. 28, 2008 |
| 7443029 |
Adhesion of copper and etch stop layer for copper alloy |
Oct. 28, 2008 |
| 7443020 |
Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit |
Oct. 28, 2008 |
| 7442969 |
Top layers of metal for high performance IC's |
Oct. 28, 2008 |
| 7442626 |
Rectangular contact used as a low voltage fuse element |
Oct. 28, 2008 |
| 7439628 |
Method for improved process latitude by elongated via integration |
Oct. 21, 2008 |
| 7439624 |
Enhanced mechanical strength via contacts |
Oct. 21, 2008 |
| 7439623 |
Semiconductor device having via connecting between interconnects |
Oct. 21, 2008 |
| 7439173 |
Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via |
Oct. 21, 2008 |
| 7439146 |
Field plated resistor with enhanced routing area thereover |
Oct. 21, 2008 |
| 7436078 |
Line layout structure of semiconductor memory device |
Oct. 14, 2008 |
| 7436069 |
Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode |
Oct. 14, 2008 |
| 7436067 |
Methods for forming conductive structures and structures regarding same |
Oct. 14, 2008 |
| 7432598 |
Semiconductor device |
Oct. 7, 2008 |
| 7432597 |
Semiconductor device and method of manufacturing the same |
Oct. 7, 2008 |
| 7432582 |
Method of forming a through-substrate interconnect |
Oct. 7, 2008 |
| 7432556 |
Semiconductor device with dummy conductors |
Oct. 7, 2008 |
| 7432189 |
Device with self aligned gaps for capacitance reduction |
Oct. 7, 2008 |
| 7429793 |
Semiconductor device having an electronic circuit disposed therein |
Sep. 30, 2008 |
| 7429789 |
Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same |
Sep. 30, 2008 |
| 7425764 |
Top layers of metal for high performance IC's |
Sep. 16, 2008 |
| 7425753 |
Semiconductor device |
Sep. 16, 2008 |
| 7425735 |
Multi-layer phase-changeable memory devices |
Sep. 16, 2008 |
| 7423346 |
Post passivation interconnection process and structures |
Sep. 9, 2008 |
| 7423345 |
Semiconductor constructions comprising a layer of metal over a substrate |
Sep. 9, 2008 |
| 7423343 |
Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof |
Sep. 9, 2008 |
| 7423340 |
Semiconductor package free of substrate and fabrication method thereof |
Sep. 9, 2008 |
| 7423304 |
Optimization of critical dimensions and pitch of patterned features in and above a substrate |
Sep. 9, 2008 |
| 7423300 |
Single-mask phase change memory element |
Sep. 9, 2008 |
| 7422975 |
Composite inter-level dielectric structure for an integrated circuit |
Sep. 9, 2008 |
| 7420279 |
Carbon containing silicon oxide film having high ashing tolerance and adhesion |
Sep. 2, 2008 |
| 7420278 |
Semiconductor device |
Sep. 2, 2008 |
| 7420277 |
System for heat dissipation in semiconductor devices |
Sep. 2, 2008 |
| 7420276 |
Post passivation structure for semiconductor chip or wafer |
Sep. 2, 2008 |
| 7420211 |
Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof |
Sep. 2, 2008 |
| 7417319 |
Semiconductor device with connecting via and dummy via and method of manufacturing the same |
Aug. 26, 2008 |
| 7417315 |
Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging |
Aug. 26, 2008 |
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