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Class Information
Number: 257/757
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > At least one layer of silicide or polycrystalline silicon > Silicide of refractory or platinum group metal
Description: Subject matter wherein a layered electrical contact or lead includes a silicide of a metal found in groups IVA, VA, VIA or VIIIA (other than iron (Fe), nickel (Ni) or cobalt (Co)) of the periodic table of the elements.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7618890 |
Methods for forming conductive structures and structures regarding same |
Nov. 17, 2009 |
| 7566651 |
Low contact resistance metal contact |
Jul. 28, 2009 |
| 7557446 |
Semiconductor device and a fabrication process thereof |
Jul. 7, 2009 |
| 7538016 |
Signal and/or ground planes with double buried insulator layers and fabrication process |
May. 26, 2009 |
| 7485569 |
Printed circuit board including embedded chips and method of fabricating the same |
Feb. 3, 2009 |
| 7479682 |
Structure of a field effect transistor having metallic silicide and manufacturing method thereof |
Jan. 20, 2009 |
| 7468557 |
Method of producing an ultra thin electrically conducting film with very low electrical resistance |
Dec. 23, 2008 |
| 7446043 |
Contact structure having silicide layers, semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device |
Nov. 4, 2008 |
| 7436067 |
Methods for forming conductive structures and structures regarding same |
Oct. 14, 2008 |
| 7432559 |
Silicide formation on SiGe |
Oct. 7, 2008 |
| 7414291 |
Semiconductor device and method of manufacturing the same |
Aug. 19, 2008 |
| 7400042 |
Substrate with adhesive bonding metallization with diffusion barrier |
Jul. 15, 2008 |
| 7378720 |
Integrated stress relief pattern and registration structure |
May. 27, 2008 |
| 7368801 |
Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same |
May. 6, 2008 |
| 7348265 |
Semiconductor device having a silicided gate electrode and method of manufacture therefor |
Mar. 25, 2008 |
| 7332435 |
Silicide structure for ultra-shallow junction for MOS devices |
Feb. 19, 2008 |
| 7294570 |
Contact integration method |
Nov. 13, 2007 |
| 7294893 |
Titanium silicide boride gate electrode |
Nov. 13, 2007 |
| 7282803 |
Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen |
Oct. 16, 2007 |
| 7279732 |
Enhanced atomic layer deposition |
Oct. 9, 2007 |
| 7271486 |
Retarding agglomeration of Ni monosilicide using Ni alloys |
Sep. 18, 2007 |
| 7244996 |
Structure of a field effect transistor having metallic silicide and manufacturing method thereof |
Jul. 17, 2007 |
| 7233037 |
Solid state imaging device and method of manufacturing the same |
Jun. 19, 2007 |
| 7224046 |
Multilayer wiring board incorporating carbon fibers and glass fibers |
May. 29, 2007 |
| 7218400 |
In-situ overlay alignment |
May. 15, 2007 |
| 7215027 |
Electrical coupling stack and processes for making same |
May. 8, 2007 |
| 7208402 |
Method and apparatus for improved power routing |
Apr. 24, 2007 |
| 7196421 |
Integrated circuit having at least one metallization level |
Mar. 27, 2007 |
| 7180189 |
Abberation mark and method for estimating overlay error and optical abberations |
Feb. 20, 2007 |
| 7180195 |
Method and apparatus for improved power routing |
Feb. 20, 2007 |
| 7173312 |
Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
Feb. 6, 2007 |
| 7160800 |
Decreasing metal-silicide oxidation during wafer queue time |
Jan. 9, 2007 |
| 7102234 |
Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy |
Sep. 5, 2006 |
| 7092273 |
Low voltage non-volatile memory transistor |
Aug. 15, 2006 |
| 7061029 |
High-voltage device structure |
Jun. 13, 2006 |
| 7053462 |
Planarization of metal container structures |
May. 30, 2006 |
| 7026692 |
Low voltage non-volatile memory transistor |
Apr. 11, 2006 |
| 7009279 |
Semiconductor device configured for suppressed germanium diffusion from a germanium-doped regions and a method for fabrication thereof |
Mar. 7, 2006 |
| 6984864 |
Semiconductor device with MISFET having low leakage current |
Jan. 10, 2006 |
| 6960832 |
Semiconductor device and its production process |
Nov. 1, 2005 |
| 6958541 |
Low gate resistance layout procedure for RF transistor devices |
Oct. 25, 2005 |
| 6940172 |
Chemical vapor deposition of titanium |
Sep. 6, 2005 |
| 6917112 |
Conductive semiconductor structures containing metal oxide regions |
Jul. 12, 2005 |
| 6909154 |
Sacrificial annealing layer for a semiconductor device and a method of fabrication |
Jun. 21, 2005 |
| 6906420 |
Semiconductor device |
Jun. 14, 2005 |
| 6905922 |
Dual fully-silicided gate MOSFETs |
Jun. 14, 2005 |
| 6885103 |
Semiconductor device including ternary phase diffusion barrier |
Apr. 26, 2005 |
| 6858904 |
High aspect ratio contact structure with reduced silicon consumption |
Feb. 22, 2005 |
| 6849909 |
Method and apparatus for weak inversion mode MOS decoupling capacitor |
Feb. 1, 2005 |
| 6841879 |
Semiconductor device |
Jan. 11, 2005 |
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