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Class Information
Number: 257/756
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > At least one layer of silicide or polycrystalline silicon > Multiple polysilicon layers
Description: Subject matter wherein a layered electrical contact or lead includes multiple polysilicon layers.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7423344 |
Bi-layer etch stop process for defect reduction and via stress migration improvement |
Sep. 9, 2008 |
| 7397124 |
Process of metal interconnects |
Jul. 8, 2008 |
| 7332811 |
Integrated circuit interconnect |
Feb. 19, 2008 |
| 7250680 |
Semiconductor circuitry constructions |
Jul. 31, 2007 |
| 7245015 |
Display apparatus |
Jul. 17, 2007 |
| 7211896 |
Semiconductor device and method of manufacturing the same |
May. 1, 2007 |
| 7151314 |
Semiconductor device with superimposed poly-silicon plugs |
Dec. 19, 2006 |
| 7119005 |
Semiconductor local interconnect and contact |
Oct. 10, 2006 |
| 7023090 |
Bonding pad and via structure design |
Apr. 4, 2006 |
| 6995411 |
Image sensor with vertically integrated thin-film photodiode |
Feb. 7, 2006 |
| 6987322 |
Contact etching utilizing multi-layer hard mask |
Jan. 17, 2006 |
| 6894364 |
Capacitor in an interconnect system and method of manufacturing thereof |
May. 17, 2005 |
| 6876045 |
Semiconductor device and process for manufacturing the same |
Apr. 5, 2005 |
| 6867474 |
Monolithic circuit inductance |
Mar. 15, 2005 |
| 6852566 |
Self-aligned rear electrode for diode array element |
Feb. 8, 2005 |
| 6833624 |
System and method for row decode in a multiport memory |
Dec. 21, 2004 |
| 6812551 |
Defect-free dielectric coatings and preparation thereof using polymeric nitrogenous porogens |
Nov. 2, 2004 |
| 6800911 |
Method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device |
Oct. 5, 2004 |
| 6783862 |
Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures |
Aug. 31, 2004 |
| 6747340 |
Multi-level shielded multi-conductor interconnect bus for MEMS |
Jun. 8, 2004 |
| 6700211 |
Method for forming conductors in semiconductor devices |
Mar. 2, 2004 |
| 6686638 |
Micromechanical component including function components suspended movably above a substrate |
Feb. 3, 2004 |
| 6611059 |
Integrated circuitry conductive lines |
Aug. 26, 2003 |
| 6599835 |
Testing dielectric and barrier layers for integrated circuit interconnects |
Jul. 29, 2003 |
| 6586838 |
Semiconductor device |
Jul. 1, 2003 |
| 6548857 |
Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process |
Apr. 15, 2003 |
| 6541865 |
Porous dielectric material and electronic devices fabricated therewith |
Apr. 1, 2003 |
| 6515328 |
Semiconductor devices with reduced control gate dimensions |
Feb. 4, 2003 |
| 6504217 |
Semiconductor device and a method of manufacturing the same |
Jan. 7, 2003 |
| 6483144 |
Semiconductor device having self-aligned contact and landing pad structure and method of forming same |
Nov. 19, 2002 |
| 6476489 |
Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure |
Nov. 5, 2002 |
| 6455935 |
Asymmetric, double-sided self-aligned silicide |
Sep. 24, 2002 |
| 6452273 |
Semiconductor integrated circuit device and method of manufacturing the same |
Sep. 17, 2002 |
| 6426284 |
Method of manufacturing wire bond pad |
Jul. 30, 2002 |
| 6351037 |
Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits |
Feb. 26, 2002 |
| 6346731 |
Semiconductor apparatus having conductive thin films |
Feb. 12, 2002 |
| 6337517 |
Semiconductor device and method of fabricating same |
Jan. 8, 2002 |
| 6310397 |
Butted contact resistance of an SRAM by double VCC implantation |
Oct. 30, 2001 |
| 6307263 |
Integrated semiconductor chip with modular dummy structures |
Oct. 23, 2001 |
| 6278186 |
Parasitic current barriers |
Aug. 21, 2001 |
| 6265777 |
Semiconductor device with a low resistance wiring layer composed of a polysilicon and a refractory metal |
Jul. 24, 2001 |
| 6252268 |
Method of forming transistors in a peripheral circuit of a semiconductor memory device |
Jun. 26, 2001 |
| 6249054 |
Semiconductor memory device with a stacked capacitance structure |
Jun. 19, 2001 |
| 6242806 |
Semiconductor device and method of manufacturing thereof |
Jun. 5, 2001 |
| 6239478 |
Semiconductor structure for a MOS transistor |
May. 29, 2001 |
| 6229212 |
Integrated circuitry and thin film transistors |
May. 8, 2001 |
| 6218723 |
Integrated capacitor with high voltage linearity and low series resistance |
Apr. 17, 2001 |
| 6166416 |
CMOS analog semiconductor apparatus and fabrication method thereof |
Dec. 26, 2000 |
| 6166440 |
Interconnection for preventing signal interference in a semiconductor device |
Dec. 26, 2000 |
| 6160297 |
Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel |
Dec. 12, 2000 |
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