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Class Information
Number: 257/754
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > At least one layer of silicide or polycrystalline silicon
Description: Subject matter wherein at least one layer of material is made up of a silicide or polycrystalline silicon.

Sub-classes under this class:

Class Number Class Name Patents
257/756 Multiple polysilicon layers 212
257/755 Polysilicon laminated with silicide 344
257/757 Silicide of refractory or platinum group metal 348

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
8710553 Method and apparatus for connecting signal lines of multiple layers to certain contacts while preventing connections with other contacts Apr. 29, 2014
8692373 Methods of forming a metal silicide region on at least one silicon structure Apr. 8, 2014
8669608 Method for manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device Mar. 11, 2014
8664761 Semiconductor structure and manufacturing method of the same Mar. 4, 2014
8648425 Resistors formed based on metal-oxide-semiconductor structures Feb. 11, 2014
8642471 Semiconductor structure and method for manufacturing the same Feb. 4, 2014
8609505 Method of forming MIM capacitor structure in FEOL Dec. 17, 2013
8598705 Composite substrate for a semiconductor chip Dec. 3, 2013
8536706 Method for fabricating semiconductor device and semiconductor device Sep. 17, 2013
8492899 Method to electrodeposit nickel on silicon for forming controllable nickel silicide Jul. 23, 2013
8476766 Semiconductor memory device and method for manufacturing the same Jul. 2, 2013
8471367 Semiconductor device and method for manufacturing semiconductor device Jun. 25, 2013
8421126 Double-sided integrated circuit chips Apr. 16, 2013
8421228 Structure and methods of forming contact structures Apr. 16, 2013
8390042 Gate etch optimization through silicon dopant profile change Mar. 5, 2013
8362575 Controlling the shape of source/drain regions in FinFETs Jan. 29, 2013
8362615 Memory and manufacturing method thereof Jan. 29, 2013
8344455 Semiconductor device and fabrication method for the same Jan. 1, 2013
8344461 Solid-state imaging device and manufacturing method for the same Jan. 1, 2013
8344509 Method for fabricating semiconductor device and semiconductor device Jan. 1, 2013
8338265 Silicided trench contact to buried conductive layer Dec. 25, 2012
8330234 Semiconductor device and manufacturing process therefor Dec. 11, 2012
8330275 Interconnect structure for semiconductor devices Dec. 11, 2012
8299499 Field effect transistor Oct. 30, 2012
8278689 Memory and interconnect design in fine pitch Oct. 2, 2012
8252680 Methods and architectures for bottomless interconnect vias Aug. 28, 2012
8222134 Self-aligned barrier layers for interconnects Jul. 17, 2012
8183145 Structure and methods of forming contact structures May. 22, 2012
8183643 Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane May. 22, 2012
8168538 Buried silicide structure and method for making May. 1, 2012
8129844 Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices Mar. 6, 2012
8125049 MIM capacitor structure in FEOL and related method Feb. 28, 2012
8110877 Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions Feb. 7, 2012
8093661 Integrated circuit device with single crystal silicon on silicide and manufacturing method Jan. 10, 2012
8089137 Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method Jan. 3, 2012
8058728 Diffusion barrier and adhesion layer for an interconnect structure Nov. 15, 2011
8053356 Interconnect structure for semiconductor devices Nov. 8, 2011
8026162 Method of manufacturing layer-stacked wiring Sep. 27, 2011
8022443 Memory and interconnect design in fine pitch Sep. 20, 2011
8022462 Methods of forming shallow trench isolation structures with buried bit lines in non-volatile memories Sep. 20, 2011
8022482 Device configuration of asymmetrical DMOSFET with schottky barrier source Sep. 20, 2011
7968956 Semiconductor device Jun. 28, 2011
7939897 Method of forming a low resistance semiconductor contact and structure therefor May. 10, 2011
7928506 Semiconductor device and method for manufacturing the same Apr. 19, 2011
7928571 Device having dual etch stop liner and reformed silicide layer and related methods Apr. 19, 2011
7919863 Semiconductor constructions Apr. 5, 2011
7910912 Semiconductor devices having a planarized insulating layer Mar. 22, 2011
7898065 Structure and method for device-specific fill for improved anneal uniformity Mar. 1, 2011
7898083 Method for low stress flip-chip assembly of fine-pitch semiconductor devices Mar. 1, 2011
7875545 Silicon-rich nickel-silicide ohmic contacts for SiC semiconductor devices Jan. 25, 2011

1 2 3 4 5 6 7 8 9 10 11 12 13

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