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Class Information
Number: 257/754
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > At least one layer of silicide or polycrystalline silicon
Description: Subject matter wherein at least one layer of material is made up of a silicide or polycrystalline silicon.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7608926 |
Nonvolatile semiconductor memory device |
Oct. 27, 2009 |
| 7592705 |
Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device |
Sep. 22, 2009 |
| 7576440 |
Semiconductor chip having bond pads and multi-chip package |
Aug. 18, 2009 |
| 7566974 |
Doped polysilicon via connecting polysilicon layers |
Jul. 28, 2009 |
| 7547977 |
Semiconductor chip having bond pads |
Jun. 16, 2009 |
| 7541682 |
Semiconductor chip having bond pads |
Jun. 2, 2009 |
| 7538016 |
Signal and/or ground planes with double buried insulator layers and fabrication process |
May. 26, 2009 |
| 7531896 |
Semiconductor device having a minimal via resistance created by applying a nitrogen plasma to a titanium via liner |
May. 12, 2009 |
| 7528430 |
Electronic systems |
May. 5, 2009 |
| 7498640 |
Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby |
Mar. 3, 2009 |
| 7495292 |
Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate |
Feb. 24, 2009 |
| 7465664 |
Method for fabricating semiconductor device to lower source/drain sheet resistance |
Dec. 16, 2008 |
| 7453159 |
Semiconductor chip having bond pads |
Nov. 18, 2008 |
| 7432559 |
Silicide formation on SiGe |
Oct. 7, 2008 |
| 7429779 |
Semiconductor device having gate electrode connection to wiring layer |
Sep. 30, 2008 |
| 7423344 |
Bi-layer etch stop process for defect reduction and via stress migration improvement |
Sep. 9, 2008 |
| 7402863 |
Trench FET with reduced mesa width and source contact inside active trench |
Jul. 22, 2008 |
| 7361597 |
Semiconductor device and method of fabricating the same |
Apr. 22, 2008 |
| 7335930 |
Borderless contact structures |
Feb. 26, 2008 |
| 7326960 |
Semiconductor circuit constructions |
Feb. 5, 2008 |
| 7327035 |
System and method for providing a low frequency filter pole |
Feb. 5, 2008 |
| 7271486 |
Retarding agglomeration of Ni monosilicide using Ni alloys |
Sep. 18, 2007 |
| 7262473 |
Metal to polysilicon contact in oxygen environment |
Aug. 28, 2007 |
| 7230337 |
Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same |
Jun. 12, 2007 |
| 7173312 |
Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
Feb. 6, 2007 |
| 7160800 |
Decreasing metal-silicide oxidation during wafer queue time |
Jan. 9, 2007 |
| 7148570 |
Low resistivity titanium silicide on heavily doped semiconductor |
Dec. 12, 2006 |
| 7148578 |
Semiconductor multi-chip package |
Dec. 12, 2006 |
| 7109556 |
Method to improve drive current by increasing the effective area of an electrode |
Sep. 19, 2006 |
| 7105443 |
Method for fabricating epitaxial cobalt-disilicide layers using cobalt-nitride thin film |
Sep. 12, 2006 |
| 7102234 |
Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy |
Sep. 5, 2006 |
| 7061115 |
Interconnect line selectively isolated from an underlying contact plug |
Jun. 13, 2006 |
| 7056794 |
FET gate structure with metal gate electrode and silicide contact |
Jun. 6, 2006 |
| 7030451 |
Method and apparatus for performing nickel salicidation |
Apr. 18, 2006 |
| 7019351 |
Transistor devices, and methods of forming transistor devices and circuit devices |
Mar. 28, 2006 |
| 7015588 |
Semiconductor device |
Mar. 21, 2006 |
| 6992388 |
Formation of micro rough polysurface for low sheet resistant salicided sub-quarter micron polylines |
Jan. 31, 2006 |
| 6992916 |
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
Jan. 31, 2006 |
| 6967408 |
Gate stack structure |
Nov. 22, 2005 |
| 6958505 |
Integrated circuit including active components and at least one passive component associated fabrication method |
Oct. 25, 2005 |
| 6943389 |
Solid-state imaging device |
Sep. 13, 2005 |
| 6936918 |
MEMS device with conductive path through substrate |
Aug. 30, 2005 |
| 6924544 |
Semiconductor device and manufacturing method of the same |
Aug. 2, 2005 |
| 6906420 |
Semiconductor device |
Jun. 14, 2005 |
| 6888252 |
Method of forming a conductive contact |
May. 3, 2005 |
| 6879042 |
Semiconductor device and method and apparatus for manufacturing the same |
Apr. 12, 2005 |
| 6861182 |
Tri-tone attenuated phase shift trim mask for double exposure alternating phase shift mask process |
Mar. 1, 2005 |
| 6861751 |
Etch stop layer for use in a self-aligned contact etch |
Mar. 1, 2005 |
| 6853032 |
Structure and method for formation of a blocked silicide resistor |
Feb. 8, 2005 |
| 6849909 |
Method and apparatus for weak inversion mode MOS decoupling capacitor |
Feb. 1, 2005 |
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