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Class Information
Number: 257/752
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Combined with electrical contact or lead > Of specified material other than unalloyed aluminum > Layered > Planarized to top of insulating layer
Description: Subject matter wherein a contact or lead and an insulating layer to which it is connected form a single planar surface.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7625816 |
Method of fabricating passivation |
Dec. 1, 2009 |
| 7589398 |
Embedded metal features structure |
Sep. 15, 2009 |
| 7585760 |
Method for forming planarizing copper in a low-k dielectric |
Sep. 8, 2009 |
| 7581314 |
Method of forming noble metal contacts |
Sep. 1, 2009 |
| 7553739 |
Integration control and reliability enhancement of interconnect air cavities |
Jun. 30, 2009 |
| 7554199 |
Substrate for evaluation |
Jun. 30, 2009 |
| 7538434 |
Copper interconnection with conductive polymer layer and method of forming the same |
May. 26, 2009 |
| 7521355 |
Integrated circuit insulators and related methods |
Apr. 21, 2009 |
| 7521779 |
Roughened printed circuit board |
Apr. 21, 2009 |
| 7485961 |
Approach to avoid buckling in BPSG by using an intermediate barrier layer |
Feb. 3, 2009 |
| 7485962 |
Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
Feb. 3, 2009 |
| 7474003 |
Semiconductor integrated circuit device |
Jan. 6, 2009 |
| 7470630 |
Approach to reduce parasitic capacitance from dummy fill |
Dec. 30, 2008 |
| 7456501 |
Semiconductor structure having recess with conductive metal |
Nov. 25, 2008 |
| 7446416 |
Barrier material formation in integrated circuit structures |
Nov. 4, 2008 |
| 7446415 |
Method for filling electrically different features |
Nov. 4, 2008 |
| 7439182 |
Semiconductor device and method of fabricating the same |
Oct. 21, 2008 |
| 7439623 |
Semiconductor device having via connecting between interconnects |
Oct. 21, 2008 |
| 7414275 |
Multi-level interconnections for an integrated circuit chip |
Aug. 19, 2008 |
| 7414314 |
Semiconductor device and manufacturing method thereof |
Aug. 19, 2008 |
| 7397122 |
Metal wiring for semiconductor device and method for forming the same |
Jul. 8, 2008 |
| 7371679 |
Semiconductor device with a metal line and method of forming the same |
May. 13, 2008 |
| 7348676 |
Semiconductor device having a metal wiring structure |
Mar. 25, 2008 |
| 7338907 |
Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications |
Mar. 4, 2008 |
| 7332813 |
Semiconductor device |
Feb. 19, 2008 |
| 7327034 |
Compositions for planarization of metal-containing surfaces using halogens and halide salts |
Feb. 5, 2008 |
| 7315082 |
Semiconductor device having integrated circuit contact |
Jan. 1, 2008 |
| 7294570 |
Contact integration method |
Nov. 13, 2007 |
| 7291920 |
Semiconductor structures |
Nov. 6, 2007 |
| 7259432 |
Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device |
Aug. 21, 2007 |
| 7250682 |
Semiconductor integrated circuit device |
Jul. 31, 2007 |
| 7235882 |
Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same |
Jun. 26, 2007 |
| 7233059 |
Semiconductor arrangement |
Jun. 19, 2007 |
| 7230335 |
Inspection methods and structures for visualizing and/or detecting specific chip structures |
Jun. 12, 2007 |
| 7227265 |
Electroplated copper interconnection structure, process for making and electroplating bath |
Jun. 5, 2007 |
| 7193323 |
Electroplated CoWP composite structures as copper barrier layers |
Mar. 20, 2007 |
| 7187085 |
Semiconductor device including dual damascene interconnections |
Mar. 6, 2007 |
| 7180188 |
Contact structure of semiconductor devices and method of fabricating the same |
Feb. 20, 2007 |
| 7176571 |
Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure |
Feb. 13, 2007 |
| 7164206 |
Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer |
Jan. 16, 2007 |
| 7161246 |
Interconnect alloys and methods and apparatus using same |
Jan. 9, 2007 |
| 7146722 |
Method of forming a bond pad structure |
Dec. 12, 2006 |
| 7145238 |
Semiconductor package and substrate having multi-level vias |
Dec. 5, 2006 |
| 7145239 |
Circuit board with trace configuration for high-speed digital differential signaling |
Dec. 5, 2006 |
| 7145244 |
Hardening of copper to improve copper CMP performance |
Dec. 5, 2006 |
| 7145245 |
Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate--therein |
Dec. 5, 2006 |
| RE39413 |
Low friction polish-stop stratum for endpointing chemical-mechanical planarization processing of semiconductor wafers |
Nov. 28, 2006 |
| 7122898 |
Electrical programmable metal resistor |
Oct. 17, 2006 |
| 7115991 |
Method for creating barriers for copper diffusion |
Oct. 3, 2006 |
| 7105925 |
Differential planarization |
Sep. 12, 2006 |
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