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Class Information
Number: 257/647
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > With means to control surface effects > Insulating coating > Insulating layer recessed into semiconductor surface (e.g., locos oxide)
Description: Subject matter wherein the insulating layer is recessed into the semiconductor surface.


Sub-classes under this class:

Class Number Class Name Patents
257/648 Combined with channel stop region in semiconductor 106


Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
4506434 Method for production of semiconductor devices Mar. 26, 1985
4507158 Trench isolated transistors in semiconductor films Mar. 26, 1985
4506437 Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Mar. 26, 1985
4502201 Semiconductor integrated circuit device and fabrication method thereof Mar. 5, 1985
4501060 Dielectrically isolated semiconductor devices Feb. 26, 1985
4495025 Process for forming grooves having different depths using a single masking step Jan. 22, 1985
4494303 Method of making dielectrically isolated silicon devices Jan. 22, 1985
4484214 pn Junction device with glass moats and a channel stopper region of greater depth than the base pn junction depth Nov. 20, 1984
4477962 Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Oct. 23, 1984
4473940 Method of producing a semiconductor device Oct. 2, 1984
4459181 Semiconductor pattern definition by selective anodization Jul. 10, 1984
4450467 Gate turn-off thyristor with selective anode penetrating shorts May. 22, 1984
RE31506 Method of manufacturing oxide isolated semiconductor device utilizing selective etching technique Jan. 24, 1984
4420874 Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns Dec. 20, 1983
4408387 Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask Oct. 11, 1983
4407696 Fabrication of isolation oxidation for MOS circuit Oct. 4, 1983
4400712 Static bipolar random access memory Aug. 23, 1983
4400411 Technique of silicon epitaxial refill Aug. 23, 1983
4396460 Method of forming groove isolation in a semiconductor device Aug. 2, 1983
4388635 High breakdown voltage semiconductor device Jun. 14, 1983
4380865 Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation Apr. 26, 1983
4369565 Method of manufacturing a semiconductor device utilizing etch and refill to form isolation regions Jan. 25, 1983
4356211 Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon Oct. 26, 1982
4356056 Process for insulating the interconnections of integrated circuits Oct. 26, 1982
4340900 Mesa epitaxial diode with oxide passivated junction and plated heat sink Jul. 20, 1982
4335501 Manufacture of monolithic LED arrays for electroluminescent display devices Jun. 22, 1982
4331708 Method of fabricating narrow deep grooves in silicon May. 25, 1982
4326332 Method of making a high density V-MOS memory array Apr. 27, 1982
4310965 Process for producing a dielectric insulator separated substrate Jan. 19, 1982
4307180 Process of forming recessed dielectric regions in a monocrystalline silicon substrate Dec. 22, 1981
4304043 Process for preparing semiconductor device _by forming reinforcing regions to facilitate separation of pellets Dec. 8, 1981
4298881 Semiconductor device with double moat and double channel stoppers Nov. 3, 1981
4295924 Method for providing self-aligned conductor in a V-groove device Oct. 20, 1981
4293588 Method of manufacturing a semiconductor device using different etch rates Oct. 6, 1981
4283235 Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation Aug. 11, 1981
4277881 Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines Jul. 14, 1981
4278705 Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide Jul. 14, 1981
4272308 Method of forming recessed isolation oxide layers Jun. 9, 1981
4271583 Fabrication of semiconductor devices having planar recessed oxide isolation region Jun. 9, 1981
4268952 Method for fabricating self-aligned high resolution non planar devices employing low resolution registration May. 26, 1981
4268537 Method for manufacturing a self-aligned contact in a grooved semiconductor surface May. 19, 1981
4264409 Contamination-free selective reactive ion etching or polycrystalline silicon against silicon dioxide Apr. 28, 1981
4255207 Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation Mar. 10, 1981
4240095 Grooving and glassivating method for semiconductor wafers Dec. 16, 1980
4238278 Polycrystalline silicon oxidation method for making shallow and deep isolation trenches Dec. 9, 1980
4236294 High performance bipolar device and method for making same Dec. 2, 1980
4236171 High power transistor having emitter pattern with symmetric lead connection pads Nov. 25, 1980
4233091 Method of manufacturing semiconductor devices having improved alignment marks Nov. 11, 1980
4231819 Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step Nov. 4, 1980
4227975 Selective plasma etching of dielectric masks in the presence of native oxides of group III-V compound semiconductors Oct. 14, 1980

1 2 3 4 5 6


 
 
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