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Class Information
Number: 257/586
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Bipolar transistor structure > With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.)
Description: Subject matter wherein the device has a non-planar upper or side surface.










Patents under this class:
1 2 3 4 5 6 7 8

Patent Number Title Of Patent Date Issued
4916083 High performance sidewall emitter transistor Apr. 10, 1990
4914049 Method of fabricating a heterojunction bipolar transistor Apr. 3, 1990
4904612 Method for manufacturing a planar, self-aligned emitter-base complex Feb. 27, 1990
4900689 Method of fabrication of isolated islands for complementary bipolar devices Feb. 13, 1990
4897703 Recessed contact bipolar transistor and method Jan. 30, 1990
4896203 Heterojunction bipolar transistor Jan. 23, 1990
4894702 High efficiency, small geometry semiconductor devices Jan. 16, 1990
4892837 Method for manufacturing semiconductor integrated circuit device Jan. 9, 1990
4889823 Bipolar transistor structure for very high speed circuits and method for the manufacture thereof Dec. 26, 1989
4887145 Semiconductor device in which electrodes are formed in a self-aligned manner Dec. 12, 1989
4883772 Process for making a self-aligned silicide shunt Nov. 28, 1989
4882294 Process for forming an epitaxial layer having portions of different thicknesses Nov. 21, 1989
4879586 Semiconductor component Nov. 7, 1989
4860077 Vertical semiconductor device having a sidewall emitter Aug. 22, 1989
4851362 Method for manufacturing a semiconductor device Jul. 25, 1989
4849364 Semiconductor devices Jul. 18, 1989
4849371 Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices Jul. 18, 1989
4847670 High performance sidewall emitter transistor Jul. 11, 1989
4825265 Transistor Apr. 25, 1989
4824799 Method of making a bipolar semiconductor device Apr. 25, 1989
4824805 Method of manufacturing semiconductor device Apr. 25, 1989
4825269 Double heterojunction inversion base transistor Apr. 25, 1989
4810668 Semiconductor device element-isolation by oxidation of polysilicon in trench Mar. 7, 1989
4808550 Method of producing isolation groove structure Feb. 28, 1989
4805004 Semiconductor device with a planar junction and self-passivating termination Feb. 14, 1989
4803176 Integrated circuit structure with active device in merged slot and method of making same Feb. 7, 1989
4797372 Method of making a merge bipolar and complementary metal oxide semiconductor transistor device Jan. 10, 1989
4771326 Composition double heterojunction transistor Sep. 13, 1988
4771013 Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice Sep. 13, 1988
4764799 Stud-defined integrated circuit structure Aug. 16, 1988
4755862 Integrated triac structure with diac control Jul. 5, 1988
4753709 Method for etching contact vias in a semiconductor device Jun. 28, 1988
4749661 Vertical slot bottom bipolar transistor structure Jun. 7, 1988
4738624 Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor Apr. 19, 1988
4725874 Semiconductor device having protected edges Feb. 16, 1988
4703554 Technique for fabricating a sidewall base contact with extrinsic base-on-insulator Nov. 3, 1987
4698127 Process for fabricating a self-aligned bipolar transistor Oct. 6, 1987
4696097 Poly-sidewall contact semiconductor device method Sep. 29, 1987
4692996 Method of fabricating semiconductor devices in dielectrically isolated silicon islands Sep. 15, 1987
4691436 Method for fabricating a bipolar semiconductor device by undercutting and local oxidation Sep. 8, 1987
4686001 Method for forming contact layer on semiconductor light emitting device Aug. 11, 1987
4663832 Method for improving the planarity and passivation in a semiconductor isolation trench arrangement May. 12, 1987
4648173 Fabrication of stud-defined integrated circuit structure Mar. 10, 1987
4641419 Fabricating an integrated circuit device having a vertical pnp transistor Feb. 10, 1987
4593305 Heterostructure bipolar transistor Jun. 3, 1986
4580331 PNP-type lateral transistor with minimal substrate operation interference and method for producing same Apr. 8, 1986
4579600 Method of making zero temperature coefficient of resistance resistors Apr. 1, 1986
4574469 Process for self-aligned buried layer, channel-stop, and isolation Mar. 11, 1986
4572765 Method of fabricating integrated circuit structures using replica patterning Feb. 25, 1986
4569698 Method of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation Feb. 11, 1986

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