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Class Information
Number: 257/521
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Integrated circuit structure with electrically isolated components > Including dielectric isolation means > Combined with pn junction isolation (e.g., isoplanar, locos) > Dielectric in groove > Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)
Description: Subject matter wherein the device has grooves for the isolation whose sides are oriented along one or more major crystal planes of the semiconductor material in which the grooves are formed.


Patents under this class:
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Patent Number Title Of Patent Date Issued
7456450 CMOS devices with hybrid channel orientations and method for fabricating the same Nov. 25, 2008
7397105 Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures Jul. 8, 2008
7382015 Semiconductor device including an element isolation portion having a recess Jun. 3, 2008
7335910 Thin film transistor, semiconductor device, display, crystallization method, and method of manufacturing thin film transistor Feb. 26, 2008
7208803 Method of forming a raised source/drain and a semiconductor device employing the same Apr. 24, 2007
7198981 Vacuum sealed surface acoustic wave pressure sensor Apr. 3, 2007
7196400 Semiconductor device with enhanced orientation ratio and method of manufacturing same Mar. 27, 2007
7183585 Semiconductor device and a method for the manufacture thereof Feb. 27, 2007
7045880 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction May. 16, 2006
6964907 Method of etching a lateral trench under an extrinsic base and improved bipolar transistor Nov. 15, 2005
6960821 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Nov. 1, 2005
6930360 Semiconductor device and manufacturing method of the same Aug. 16, 2005
6903368 Thin-film transistor device, its manufacturing process, and image display using the device Jun. 7, 2005
6897095 Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode May. 24, 2005
6882026 Semiconductor apparatus and process for producing the same, and process for making via hole Apr. 19, 2005
6864534 Semiconductor wafer Mar. 8, 2005
6836001 Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench Dec. 28, 2004
6798038 Manufacturing method of semiconductor device with filling insulating film into trench Sep. 28, 2004
6787877 Method for filling structural gaps and integrated circuitry Sep. 7, 2004
6750516 Systems and methods for electrically isolating portions of wafers Jun. 15, 2004
6686642 Multi-level integrated circuit for wide-gap substrate bonding Feb. 3, 2004
6680520 Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses Jan. 20, 2004
6639280 Semiconductor device and semiconductor chip using SOI substrate Oct. 28, 2003
6614073 SEMICONDUCTOR CHIP WITH A BASE ELECTRODE AND AN EMITTER ELECTRODE EXPOSED ON ONE OF A PAIR OF OPPOSITE LATERAL FACES AND A COLLECTOR ELECTRODE EXPOSED ON A REMAINING ONE OF THE PAIR OF THE OPP Sep. 2, 2003
6537895 Method of forming shallow trench isolation in a silicon wafer Mar. 25, 2003
6528858 MOSFETs with differing gate dielectrics and method of formation Mar. 4, 2003
6525403 Semiconductor device having MIS field effect transistors or three-dimensional structure Feb. 25, 2003
6433402 Selective copper alloy deposition Aug. 13, 2002
6424048 Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them Jul. 23, 2002
6417571 Single grain copper interconnect with bamboo structure in a trench Jul. 9, 2002
6285073 Contact structure and method of formation Sep. 4, 2001
6242788 Semiconductor device and a method of manufacturing the same Jun. 5, 2001
6214698 Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer Apr. 10, 2001
6040597 Isolation boundaries in flash memory cores Mar. 21, 2000
5854509 Method of fabricating semiconductor device and semiconductor device Dec. 29, 1998
5591665 Process for producing a semiconductor structure including a plurality of vertical semiconductor devices and at least one lateral semiconductor device integrated in a semiconductor body Jan. 7, 1997
5587612 Semiconductor device having semiconductor active and dummy regions with the dummy regions lower in height than the active regions Dec. 24, 1996
5583368 Stacked devices Dec. 10, 1996
5548154 Isoplanar isolated active regions Aug. 20, 1996
5539241 Monolithic passive component Jul. 23, 1996
5468978 Forming B.sub.1-x C.sub.x semiconductor devices by chemical vapor deposition Nov. 21, 1995
5401998 Trench isolation using doped sidewalls Mar. 28, 1995
5306950 Electrode assembly for a semiconductor device Apr. 26, 1994
5250837 Method for dielectrically isolating integrated circuits using doped oxide sidewalls Oct. 5, 1993
4807012 IC which eliminates support bias influence on dielectrically isolated components Feb. 21, 1989
4670769 Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation Jun. 2, 1987
4635090 Tapered groove IC isolation Jan. 6, 1987
4608582 Semiconductor device having non-saturating I-V characteristics and integrated circuit structure including same Aug. 26, 1986
4569698 Method of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation Feb. 11, 1986
RE31937 Semiconductor device and method for its preparation Jul. 2, 1985

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