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Class Information
Number: 257/519
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Integrated circuit structure with electrically isolated components > Including dielectric isolation means > Combined with pn junction isolation (e.g., isoplanar, locos) > Dielectric in groove > Including heavily doped channel stop region adjacent groove
Description: Subject matter wherein the device has at least one heavily doped semiconductor region adjacent a dielectric filled groove to prevent formation of parasitic inversion channels in the semiconductor material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7443007 |
Trench isolation structure having an implanted buffer layer |
Oct. 28, 2008 |
| 7425752 |
Semiconductor device channel termination |
Sep. 16, 2008 |
| 7382015 |
Semiconductor device including an element isolation portion having a recess |
Jun. 3, 2008 |
| 7271468 |
High-voltage compatible, full-depleted CCD |
Sep. 18, 2007 |
| 7221035 |
Semiconductor structure avoiding poly stringer formation |
May. 22, 2007 |
| 7166906 |
Package with barrier wall and method for manufacturing the same |
Jan. 23, 2007 |
| 7071515 |
Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
Jul. 4, 2006 |
| 7071531 |
Trench isolation for semiconductor devices |
Jul. 4, 2006 |
| 7053459 |
Semiconductor integrated circuit device and process for producing the same |
May. 30, 2006 |
| 7019379 |
Semiconductor device comprising voltage regulator element |
Mar. 28, 2006 |
| 7009271 |
Memory device with an alternating Vss interconnection |
Mar. 7, 2006 |
| 6958521 |
Shallow trench isolation structure |
Oct. 25, 2005 |
| 6953961 |
DRAM structure and fabricating method thereof |
Oct. 11, 2005 |
| 6940145 |
Termination structure for a semiconductor device |
Sep. 6, 2005 |
| 6897112 |
Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related semiconductor configuration, and related memory unit |
May. 24, 2005 |
| 6894354 |
Trench isolated transistors, trench isolation structures, memory cells, and DRAMs |
May. 17, 2005 |
| 6856001 |
Trench isolation for semiconductor devices |
Feb. 15, 2005 |
| 6849519 |
Method of forming an isolation layer in a semiconductor devices |
Feb. 1, 2005 |
| 6815714 |
Conductive structure in a semiconductor material |
Nov. 9, 2004 |
| 6812486 |
Conductive structure and method of forming the structure |
Nov. 2, 2004 |
| 6740954 |
Semiconductor device reducing junction leakage current and narrow width effect |
May. 25, 2004 |
| 6737724 |
Semiconductor device and method of manufacturing the same |
May. 18, 2004 |
| 6586804 |
Shallow trench isolation type semiconductor device and method of manufacturing the same |
Jul. 1, 2003 |
| 6525403 |
Semiconductor device having MIS field effect transistors or three-dimensional structure |
Feb. 25, 2003 |
| 6518635 |
Semiconductor device and manufacturing method thereof |
Feb. 11, 2003 |
| 6504226 |
Thin-film transistor used as heating element for microreaction chamber |
Jan. 7, 2003 |
| 6501155 |
Semiconductor apparatus and process for manufacturing the same |
Dec. 31, 2002 |
| 6479875 |
Fabrication of semiconductor gettering structures by ion implantation |
Nov. 12, 2002 |
| 6445048 |
Semiconductor configuration having trenches for isolating doped regions |
Sep. 3, 2002 |
| 6384455 |
MOS semiconductor device with shallow trench isolation structure and manufacturing method thereof |
May. 7, 2002 |
| 6369433 |
High voltage transistor with low body effect and low leakage |
Apr. 9, 2002 |
| 6262467 |
Etch barrier structure of a semiconductor device and method for fabricating the same |
Jul. 17, 2001 |
| 6232639 |
Method and structure to reduce latch-up using edge implants |
May. 15, 2001 |
| 6188113 |
High voltage transistor with high gated diode breakdown, low body effect and low leakage |
Feb. 13, 2001 |
| 6110803 |
Method for fabricating a high-bias device |
Aug. 29, 2000 |
| 6084276 |
Threshold voltage tailoring of corner of MOSFET device |
Jul. 4, 2000 |
| 6051870 |
Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxide dielectric film |
Apr. 18, 2000 |
| 6046483 |
Planar isolation structure in an integrated circuit |
Apr. 4, 2000 |
| 6037647 |
Semiconductor device having an epitaxial substrate and a fabrication process thereof |
Mar. 14, 2000 |
| 6034410 |
MOSFET structure with planar surface |
Mar. 7, 2000 |
| 6005279 |
Trench edge spacer formation |
Dec. 21, 1999 |
| 5874769 |
Mosfet isolation structure with planar surface |
Feb. 23, 1999 |
| 5844270 |
Flash memory device and manufacturing method therefor |
Dec. 1, 1998 |
| 5841169 |
Integrated circuit containing devices dielectrically isolated and junction isolated from a substrate |
Nov. 24, 1998 |
| 5729043 |
Shallow trench isolation with self aligned PSG layer |
Mar. 17, 1998 |
| 5696399 |
Process for manufacturing MOS-type integrated circuits |
Dec. 9, 1997 |
| 5675176 |
Semiconductor device and a method for manufacturing the same |
Oct. 7, 1997 |
| 5640041 |
Stress relaxation in dielectric before metallization |
Jun. 17, 1997 |
| 5635753 |
Integrated circuit |
Jun. 3, 1997 |
| 5598022 |
Optical semiconductor device |
Jan. 28, 1997 |
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